{"id":"https://openalex.org/W2100708447","doi":"https://doi.org/10.1109/iscas.2011.5938043","title":"Clock distribution models of 3-D integrated systems","display_name":"Clock distribution models of 3-D integrated systems","publication_year":2011,"publication_date":"2011-05-01","ids":{"openalex":"https://openalex.org/W2100708447","doi":"https://doi.org/10.1109/iscas.2011.5938043","mag":"2100708447"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2011.5938043","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2011.5938043","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE International Symposium of Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5059641297","display_name":"Ioannis Savidis","orcid":"https://orcid.org/0000-0003-4230-1795"},"institutions":[{"id":"https://openalex.org/I5388228","display_name":"University of Rochester","ror":"https://ror.org/022kthw22","country_code":"US","type":"education","lineage":["https://openalex.org/I5388228"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ioannis Savidis","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Rochester, Rochester, NY, USA","Department of Electrical and Computer Engineering, University of Rochester, NY 14627, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Rochester, Rochester, NY, USA","institution_ids":["https://openalex.org/I5388228"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Rochester, NY 14627, USA","institution_ids":["https://openalex.org/I5388228"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031542707","display_name":"Vasilis F. Pavlidis","orcid":"https://orcid.org/0000-0002-4063-4652"},"institutions":[{"id":"https://openalex.org/I5388228","display_name":"University of Rochester","ror":"https://ror.org/022kthw22","country_code":"US","type":"education","lineage":["https://openalex.org/I5388228"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Vasilis Pavlidis","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Rochester, Rochester, NY, USA","Department of Electrical and Computer Engineering, University of Rochester, NY 14627, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Rochester, Rochester, NY, USA","institution_ids":["https://openalex.org/I5388228"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Rochester, NY 14627, USA","institution_ids":["https://openalex.org/I5388228"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5053517349","display_name":"Eby G. Friedman","orcid":"https://orcid.org/0000-0002-5549-7160"},"institutions":[{"id":"https://openalex.org/I5388228","display_name":"University of Rochester","ror":"https://ror.org/022kthw22","country_code":"US","type":"education","lineage":["https://openalex.org/I5388228"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Eby G. Friedman","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Rochester, Rochester, NY, USA","Department of Electrical and Computer Engineering, University of Rochester, NY 14627, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Rochester, Rochester, NY, USA","institution_ids":["https://openalex.org/I5388228"]},{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Rochester, NY 14627, USA","institution_ids":["https://openalex.org/I5388228"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I5388228"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.19125947,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"2225","last_page":"2228"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11444","display_name":"Electromagnetic Compatibility and Noise Suppression","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.7960211634635925},{"id":"https://openalex.org/keywords/inductance","display_name":"Inductance","score":0.7115258574485779},{"id":"https://openalex.org/keywords/capacitance","display_name":"Capacitance","score":0.6645594239234924},{"id":"https://openalex.org/keywords/electrical-impedance","display_name":"Electrical impedance","score":0.5649399161338806},{"id":"https://openalex.org/keywords/equivalent-series-inductance","display_name":"Equivalent series inductance","score":0.5594759583473206},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5426607131958008},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.5189347267150879},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4973044693470001},{"id":"https://openalex.org/keywords/equivalent-circuit","display_name":"Equivalent circuit","score":0.4258931875228882},{"id":"https://openalex.org/keywords/equivalent-series-resistance","display_name":"Equivalent series resistance","score":0.4241000711917877},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.25766947865486145},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.21582567691802979},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.18389439582824707}],"concepts":[{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.7960211634635925},{"id":"https://openalex.org/C29210110","wikidata":"https://www.wikidata.org/wiki/Q177897","display_name":"Inductance","level":3,"score":0.7115258574485779},{"id":"https://openalex.org/C30066665","wikidata":"https://www.wikidata.org/wiki/Q164399","display_name":"Capacitance","level":3,"score":0.6645594239234924},{"id":"https://openalex.org/C17829176","wikidata":"https://www.wikidata.org/wiki/Q179043","display_name":"Electrical impedance","level":2,"score":0.5649399161338806},{"id":"https://openalex.org/C141490761","wikidata":"https://www.wikidata.org/wiki/Q5384728","display_name":"Equivalent series inductance","level":4,"score":0.5594759583473206},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5426607131958008},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.5189347267150879},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4973044693470001},{"id":"https://openalex.org/C23572009","wikidata":"https://www.wikidata.org/wiki/Q964981","display_name":"Equivalent circuit","level":3,"score":0.4258931875228882},{"id":"https://openalex.org/C14485415","wikidata":"https://www.wikidata.org/wiki/Q5384730","display_name":"Equivalent series resistance","level":3,"score":0.4241000711917877},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.25766947865486145},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.21582567691802979},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.18389439582824707},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C17525397","wikidata":"https://www.wikidata.org/wiki/Q176140","display_name":"Electrode","level":2,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":4,"locations":[{"id":"doi:10.1109/iscas.2011.5938043","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2011.5938043","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE International Symposium of Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.300.9622","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.300.9622","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.ece.rochester.edu/users/friedman/papers/ISCAS_11.pdf","raw_type":"text"},{"id":"pmh:oai:pure.atira.dk:openaire_cris_publications/56fde15b-1126-431f-9e7b-4cc84e356ddc","is_oa":false,"landing_page_url":"https://research.manchester.ac.uk/en/publications/56fde15b-1126-431f-9e7b-4cc84e356ddc","pdf_url":null,"source":{"id":"https://openalex.org/S4306400662","display_name":"Research Explorer (The University of Manchester)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I28407311","host_organization_name":"University of Manchester","host_organization_lineage":["https://openalex.org/I28407311"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Savidis, I, Pavlidis, V & Friedman, E G 2011, Clock distribution models of 3-D integrated systems. in Proceedings - IEEE International Symposium on Circuits and Systems|Proc IEEE Int Symp Circuits Syst. IEEE, pp. 2225-2228, 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011, Rio de Janeiro, 1/07/11. https://doi.org/10.1109/ISCAS.2011.5938043","raw_type":"info:eu-repo/semantics/conferenceObject"},{"id":"pmh:oai:pure.atira.dk:publications/56fde15b-1126-431f-9e7b-4cc84e356ddc","is_oa":false,"landing_page_url":"https://www.research.manchester.ac.uk/portal/en/publications/clock-distribution-models-of-3d-integrated-systems(56fde15b-1126-431f-9e7b-4cc84e356ddc).html","pdf_url":null,"source":{"id":"https://openalex.org/S4306400662","display_name":"Research Explorer (The University of Manchester)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I28407311","host_organization_name":"University of Manchester","host_organization_lineage":["https://openalex.org/I28407311"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Savidis, I, Pavlidis, V & Friedman, E G 2011, Clock distribution models of 3-D integrated systems. in Proceedings - IEEE International Symposium on Circuits and Systems|Proc IEEE Int Symp Circuits Syst. IEEE, pp. 2225-2228, 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011, Rio de Janeiro, 1/07/11. https://doi.org/10.1109/ISCAS.2011.5938043","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5199999809265137,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1556480701","https://openalex.org/W1949438111","https://openalex.org/W2026717319","https://openalex.org/W2055510065","https://openalex.org/W2109314689","https://openalex.org/W2129785295","https://openalex.org/W2130324138","https://openalex.org/W2131239505","https://openalex.org/W2137807823","https://openalex.org/W2145135695","https://openalex.org/W2481508967"],"related_works":["https://openalex.org/W3205678237","https://openalex.org/W2039404188","https://openalex.org/W2371924276","https://openalex.org/W2949499314","https://openalex.org/W2074913316","https://openalex.org/W2365402110","https://openalex.org/W2349179171","https://openalex.org/W2166925515","https://openalex.org/W2150174618","https://openalex.org/W2054221486"],"abstract_inverted_index":{"Clock":[0],"distribution":[1],"topologies":[2,16],"in":[3],"a":[4,48],"three-tier":[5],"3-D":[6,33],"integrated":[7],"circuit":[8],"are":[9,17,57],"explored.":[10],"Models":[11],"of":[12,31,41,47],"three":[13],"different":[14],"clock":[15],"applied":[18],"to":[19,23,59],"determine":[20],"the":[21,29,32,42],"root":[22],"leaf":[24],"delay.":[25],"The":[26,53],"models":[27],"incorporate":[28],"impedance":[30],"via":[34,51],"between":[35,64],"planes":[36],"based":[37],"on":[38],"closed-form":[39],"expressions":[40],"resistance,":[43],"inductance,":[44],"and":[45,66],"capacitance":[46],"through":[49],"silicon":[50],"(TSV).":[52],"resulting":[54],"modeled":[55],"delays":[56],"compared":[58],"experimental":[60,67],"data.":[61],"Good":[62],"agreement":[63],"simulation":[65],"data":[68],"is":[69],"achieved.":[70]},"counts_by_year":[{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1}],"updated_date":"2026-08-01T09:00:35.917206","created_date":"2025-10-10T00:00:00"}
