{"id":"https://openalex.org/W2132075265","doi":"https://doi.org/10.1109/iscas.2011.5937789","title":"Register On MEsh (ROME): A novel approach for clock mesh network synthesis","display_name":"Register On MEsh (ROME): A novel approach for clock mesh network synthesis","publication_year":2011,"publication_date":"2011-05-01","ids":{"openalex":"https://openalex.org/W2132075265","doi":"https://doi.org/10.1109/iscas.2011.5937789","mag":"2132075265"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2011.5937789","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2011.5937789","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE International Symposium of Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5029213009","display_name":"Jianchao Lu","orcid":null},"institutions":[{"id":"https://openalex.org/I72816309","display_name":"Drexel University","ror":"https://ror.org/04bdffz58","country_code":"US","type":"education","lineage":["https://openalex.org/I72816309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jianchao Lu","raw_affiliation_strings":["Electrical and Computer Engineering, Drexel University, Philadelphia, PA 19104, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering, Drexel University, Philadelphia, PA 19104, USA","institution_ids":["https://openalex.org/I72816309"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5077110071","display_name":"Yusuf Ak\u015fehir","orcid":null},"institutions":[{"id":"https://openalex.org/I134235054","display_name":"Sabanc\u0131 \u00dcniversitesi","ror":"https://ror.org/049asqa32","country_code":"TR","type":"education","lineage":["https://openalex.org/I134235054"]}],"countries":["TR"],"is_corresponding":false,"raw_author_name":"Yusuf Aksehir","raw_affiliation_strings":["Electronics Engineering, Sabanci University, Istanbul 34956, Turkey"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electronics Engineering, Sabanci University, Istanbul 34956, Turkey","institution_ids":["https://openalex.org/I134235054"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5081080799","display_name":"Bar\u0131\u015f Ta\u015fk\u0131n","orcid":"https://orcid.org/0000-0002-7631-5696"},"institutions":[{"id":"https://openalex.org/I72816309","display_name":"Drexel University","ror":"https://ror.org/04bdffz58","country_code":"US","type":"education","lineage":["https://openalex.org/I72816309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Baris Taskin","raw_affiliation_strings":["Electrical and Computer Engineering, Drexel University, Philadelphia, PA 19104, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering, Drexel University, Philadelphia, PA 19104, USA","institution_ids":["https://openalex.org/I72816309"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1219","last_page":"1222"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6916487216949463},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6795289516448975},{"id":"https://openalex.org/keywords/shared-mesh","display_name":"Shared mesh","score":0.6119745373725891},{"id":"https://openalex.org/keywords/timing-failure","display_name":"Timing failure","score":0.6046308279037476},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.601620078086853},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.6001327037811279},{"id":"https://openalex.org/keywords/switched-mesh","display_name":"Switched mesh","score":0.562582790851593},{"id":"https://openalex.org/keywords/clock-network","display_name":"Clock network","score":0.5544678568840027},{"id":"https://openalex.org/keywords/mesh-networking","display_name":"Mesh networking","score":0.5361798405647278},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.4949461817741394},{"id":"https://openalex.org/keywords/stub","display_name":"Stub (electronics)","score":0.492121160030365},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.4508957862854004},{"id":"https://openalex.org/keywords/wireless-mesh-network","display_name":"Wireless mesh network","score":0.34275004267692566},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.1811845302581787},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1745690405368805},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.14401334524154663},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.13926735520362854},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09539744257926941}],"concepts":[{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6916487216949463},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6795289516448975},{"id":"https://openalex.org/C37427157","wikidata":"https://www.wikidata.org/wiki/Q7489552","display_name":"Shared mesh","level":5,"score":0.6119745373725891},{"id":"https://openalex.org/C104654189","wikidata":"https://www.wikidata.org/wiki/Q7806740","display_name":"Timing failure","level":5,"score":0.6046308279037476},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.601620078086853},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.6001327037811279},{"id":"https://openalex.org/C165323707","wikidata":"https://www.wikidata.org/wiki/Q7659102","display_name":"Switched mesh","level":5,"score":0.562582790851593},{"id":"https://openalex.org/C2778182565","wikidata":"https://www.wikidata.org/wiki/Q1752879","display_name":"Clock network","level":5,"score":0.5544678568840027},{"id":"https://openalex.org/C123691950","wikidata":"https://www.wikidata.org/wiki/Q25552104","display_name":"Mesh networking","level":3,"score":0.5361798405647278},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.4949461817741394},{"id":"https://openalex.org/C63676506","wikidata":"https://www.wikidata.org/wiki/Q3976238","display_name":"Stub (electronics)","level":2,"score":0.492121160030365},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.4508957862854004},{"id":"https://openalex.org/C31548570","wikidata":"https://www.wikidata.org/wiki/Q6453712","display_name":"Wireless mesh network","level":4,"score":0.34275004267692566},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.1811845302581787},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1745690405368805},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.14401334524154663},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.13926735520362854},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09539744257926941},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C108037233","wikidata":"https://www.wikidata.org/wiki/Q11375","display_name":"Wireless network","level":3,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2011.5937789","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2011.5937789","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE International Symposium of Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8999999761581421}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W1540004773","https://openalex.org/W1979163729","https://openalex.org/W1985843314","https://openalex.org/W2032024709","https://openalex.org/W2032842232","https://openalex.org/W2041950850","https://openalex.org/W2076139224","https://openalex.org/W2121252299","https://openalex.org/W2125692303","https://openalex.org/W2128237591","https://openalex.org/W2133916137","https://openalex.org/W2144758504","https://openalex.org/W2149199452","https://openalex.org/W2163899785","https://openalex.org/W3143262395","https://openalex.org/W4230442644","https://openalex.org/W4254534263","https://openalex.org/W6632308595"],"related_works":["https://openalex.org/W2088914741","https://openalex.org/W4247180033","https://openalex.org/W2559451387","https://openalex.org/W2199871724","https://openalex.org/W2144282137","https://openalex.org/W2803012234","https://openalex.org/W4251300178","https://openalex.org/W2087612346","https://openalex.org/W2151287729","https://openalex.org/W2617666058"],"abstract_inverted_index":{"A":[0],"clock":[1,57,82,96],"mesh":[2,14,20,68,83],"network":[3],"synthesis":[4],"and":[5,22,59,86],"optimization":[6],"flow":[7],"is":[8,29,89,107],"proposed":[9,27],"which":[10,39,62],"entails":[11],"the":[12,34,41,77,81,104],"optimal":[13],"size":[15],"selection,":[16],"incremental":[17],"register":[18],"placement,":[19],"reduction":[21],"buffer":[23],"driver":[24],"insertion.":[25],"The":[26,49,99],"method":[28,42],"based":[30],"on":[31,36,46,80,111],"incrementally":[32],"placing":[33],"registers":[35,71],"a":[37,66,94],"mesh,":[38],"gives":[40],"its":[43],"name":[44],"\"Register":[45],"MEsh":[47],"(ROME)\".":[48],"primary":[50],"objectives":[51],"of":[52,103],"ROME":[53],"are":[54,63],"low":[55],"global":[56],"skew":[58,97],"power":[60,101],"dissipation,":[61],"achieved":[64],"through":[65],"sparse":[67],"implementation":[69],"with":[70,93],"mesh.":[72],"Experimental":[73],"results":[74],"show":[75],"that":[76],"total":[78,100],"wirelength":[79],"(grid":[84],"wires":[85],"stub":[87],"wires)":[88],"reduced":[90,108],"by":[91,109],"36.1%":[92],"2.8ps":[95],"improvement.":[98],"consumption":[102],"experimented":[105],"circuits":[106],"14.1%":[110],"average.":[112]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":2},{"year":2016,"cited_by_count":1},{"year":2014,"cited_by_count":2},{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}