{"id":"https://openalex.org/W2125254568","doi":"https://doi.org/10.1109/iscas.2011.5937723","title":"A parallel and area-efficient architecture for deblocking filter and Adaptive Loop Filter","display_name":"A parallel and area-efficient architecture for deblocking filter and Adaptive Loop Filter","publication_year":2011,"publication_date":"2011-05-01","ids":{"openalex":"https://openalex.org/W2125254568","doi":"https://doi.org/10.1109/iscas.2011.5937723","mag":"2125254568"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2011.5937723","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2011.5937723","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE International Symposium of Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100761226","display_name":"Juan Du","orcid":"https://orcid.org/0000-0003-2165-1112"},"institutions":[{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Juan Du","raw_affiliation_strings":["Institute of Information and Communication Engineering, Key Laboratory of Integrated Information Network Technology of Zhejiang Province, University of Zhejiang, Hangzhou, China","Institute of Information and Communication Engineering, Key Laboratory of Integrated Information Network Technology of Zhejiang Province, Zhejiang University, Hangzhou, 310027, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Information and Communication Engineering, Key Laboratory of Integrated Information Network Technology of Zhejiang Province, University of Zhejiang, Hangzhou, China","institution_ids":[]},{"raw_affiliation_string":"Institute of Information and Communication Engineering, Key Laboratory of Integrated Information Network Technology of Zhejiang Province, Zhejiang University, Hangzhou, 310027, China","institution_ids":["https://openalex.org/I76130692"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5106403416","display_name":"Lu Yu","orcid":"https://orcid.org/0000-0002-0550-7754"},"institutions":[{"id":"https://openalex.org/I76130692","display_name":"Zhejiang University","ror":"https://ror.org/00a2xv884","country_code":"CN","type":"education","lineage":["https://openalex.org/I76130692"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Lu Yu","raw_affiliation_strings":["Institute of Information and Communication Engineering, Key Laboratory of Integrated Information Network Technology of Zhejiang Province, University of Zhejiang, Hangzhou, China","Institute of Information and Communication Engineering, Key Laboratory of Integrated Information Network Technology of Zhejiang Province, Zhejiang University, Hangzhou, 310027, China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Information and Communication Engineering, Key Laboratory of Integrated Information Network Technology of Zhejiang Province, University of Zhejiang, Hangzhou, China","institution_ids":[]},{"raw_affiliation_string":"Institute of Information and Communication Engineering, Key Laboratory of Integrated Information Network Technology of Zhejiang Province, Zhejiang University, Hangzhou, 310027, China","institution_ids":["https://openalex.org/I76130692"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I76130692"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":"3","issue":null,"first_page":"945","last_page":"948"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10741","display_name":"Video Coding and Compression Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10741","display_name":"Video Coding and Compression Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10901","display_name":"Advanced Data Compression Techniques","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11165","display_name":"Image and Video Quality Assessment","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/deblocking-filter","display_name":"Deblocking filter","score":0.9896172881126404},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7886637449264526},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6859722137451172},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.6825069785118103},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.5415816903114319},{"id":"https://openalex.org/keywords/filter","display_name":"Filter (signal processing)","score":0.5227230191230774},{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.5219385027885437},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.49089962244033813},{"id":"https://openalex.org/keywords/coding","display_name":"Coding (social sciences)","score":0.48246532678604126},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.42977219820022583},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4194740056991577},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4188097417354584},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4071386456489563},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.15227338671684265},{"id":"https://openalex.org/keywords/computer-vision","display_name":"Computer vision","score":0.09369441866874695}],"concepts":[{"id":"https://openalex.org/C143184774","wikidata":"https://www.wikidata.org/wiki/Q3020846","display_name":"Deblocking filter","level":2,"score":0.9896172881126404},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7886637449264526},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6859722137451172},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.6825069785118103},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.5415816903114319},{"id":"https://openalex.org/C106131492","wikidata":"https://www.wikidata.org/wiki/Q3072260","display_name":"Filter (signal processing)","level":2,"score":0.5227230191230774},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.5219385027885437},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.49089962244033813},{"id":"https://openalex.org/C179518139","wikidata":"https://www.wikidata.org/wiki/Q5140297","display_name":"Coding (social sciences)","level":2,"score":0.48246532678604126},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.42977219820022583},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4194740056991577},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4188097417354584},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4071386456489563},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.15227338671684265},{"id":"https://openalex.org/C31972630","wikidata":"https://www.wikidata.org/wiki/Q844240","display_name":"Computer vision","level":1,"score":0.09369441866874695},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2011.5937723","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2011.5937723","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE International Symposium of Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W832984975","https://openalex.org/W2125117597","https://openalex.org/W2127370302","https://openalex.org/W2134927288","https://openalex.org/W2593030302","https://openalex.org/W6678473783"],"related_works":["https://openalex.org/W2387264083","https://openalex.org/W2604877941","https://openalex.org/W1669114967","https://openalex.org/W2125591518","https://openalex.org/W2559991806","https://openalex.org/W2390885485","https://openalex.org/W2362523726","https://openalex.org/W2370747590","https://openalex.org/W2972757702","https://openalex.org/W4242191701"],"abstract_inverted_index":{"Adaptive":[0],"Loop":[1],"Filter":[2],"(ALF)":[3],"has":[4],"been":[5],"developed":[6],"lately":[7],"to":[8],"improve":[9],"the":[10,46],"video":[11],"coding":[12],"performance.":[13],"It":[14],"is":[15,88],"inserted":[16],"between":[17],"deblocking":[18,23,42,53],"and":[19,24,43,54,76,93],"inter-prediction,":[20],"which":[21],"makes":[22],"ALF":[25,44,55],"very":[26],"time-critical":[27],"because":[28],"they":[29],"are":[30,68],"conducted":[31],"sequentially.":[32],"In":[33],"this":[34],"paper,":[35],"we":[36],"propose":[37],"an":[38],"efficient":[39],"architecture":[40,49,75,87],"integrating":[41],"for":[45,98],"decoder.":[47],"The":[48,85],"not":[50],"only":[51],"implements":[52],"in":[56,90,108],"parallel":[57,78],"but":[58],"also":[59],"reduces":[60],"area":[61],"cost":[62],"as":[63,65],"much":[64],"possible.":[66],"These":[67],"achieved":[69],"by":[70,104],"shared":[71],"hybrid":[72],"organized":[73],"memory":[74],"one-block-two-edge":[77],"strategy":[79],"using":[80],"a":[81,109],"novel":[82],"filter":[83],"order.":[84],"proposed":[86],"implemented":[89],"verilog":[91],"HDL":[92],"can":[94],"achieve":[95],"real-time":[96],"decoding":[97],"1080p":[99],"@":[100],"30":[101],"fps":[102],"applications":[103],"working":[105],"at":[106],"211MHz":[107],"Xilinx":[110],"Virtex-5":[111],"FPGA.":[112]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":1},{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
