{"id":"https://openalex.org/W2145541501","doi":"https://doi.org/10.1109/iscas.2011.5937653","title":"Asynchronous-QDI 2D IIR digital filter circuits","display_name":"Asynchronous-QDI 2D IIR digital filter circuits","publication_year":2011,"publication_date":"2011-05-01","ids":{"openalex":"https://openalex.org/W2145541501","doi":"https://doi.org/10.1109/iscas.2011.5937653","mag":"2145541501"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2011.5937653","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2011.5937653","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE International Symposium of Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5051533479","display_name":"Nilanka Rajapaksha","orcid":null},"institutions":[{"id":"https://openalex.org/I110152177","display_name":"University of Akron","ror":"https://ror.org/02kyckx55","country_code":"US","type":"education","lineage":["https://openalex.org/I110152177"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Nilanka T. Rajapaksha","raw_affiliation_strings":["ECE, University of Akron, Akron, OH, USA","ECE, Univ. of Akron, OH 44325-3904, USA"],"affiliations":[{"raw_affiliation_string":"ECE, University of Akron, Akron, OH, USA","institution_ids":["https://openalex.org/I110152177"]},{"raw_affiliation_string":"ECE, Univ. of Akron, OH 44325-3904, USA","institution_ids":["https://openalex.org/I110152177"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5064035420","display_name":"Arjuna Madanayake","orcid":null},"institutions":[{"id":"https://openalex.org/I110152177","display_name":"University of Akron","ror":"https://ror.org/02kyckx55","country_code":"US","type":"education","lineage":["https://openalex.org/I110152177"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Arjuna Madanayake","raw_affiliation_strings":["ECE, University of Akron, Akron, OH, USA","ECE, Univ. of Akron, OH 44325-3904, USA"],"affiliations":[{"raw_affiliation_string":"ECE, University of Akron, Akron, OH, USA","institution_ids":["https://openalex.org/I110152177"]},{"raw_affiliation_string":"ECE, Univ. of Akron, OH 44325-3904, USA","institution_ids":["https://openalex.org/I110152177"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5051533479"],"corresponding_institution_ids":["https://openalex.org/I110152177"],"apc_list":null,"apc_paid":null,"fwci":0.2098,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.59654361,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"130","issue":null,"first_page":"665","last_page":"668"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/infinite-impulse-response","display_name":"Infinite impulse response","score":0.830284833908081},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.8242735862731934},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6851556897163391},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.6851155757904053},{"id":"https://openalex.org/keywords/realization","display_name":"Realization (probability)","score":0.6059374809265137},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.5481132864952087},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.49822998046875},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4863305687904358},{"id":"https://openalex.org/keywords/digital-filter","display_name":"Digital filter","score":0.4807286262512207},{"id":"https://openalex.org/keywords/2d-filters","display_name":"2D Filters","score":0.4602256417274475},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.4569646716117859},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.45308154821395874},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3888593912124634},{"id":"https://openalex.org/keywords/filter","display_name":"Filter (signal processing)","score":0.351131796836853},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.3041379451751709},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.2659471035003662},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.22232922911643982},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1481245458126068},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.10332179069519043},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.09654304385185242},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.08152565360069275}],"concepts":[{"id":"https://openalex.org/C183816354","wikidata":"https://www.wikidata.org/wiki/Q665617","display_name":"Infinite impulse response","level":4,"score":0.830284833908081},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.8242735862731934},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6851556897163391},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.6851155757904053},{"id":"https://openalex.org/C2781089630","wikidata":"https://www.wikidata.org/wiki/Q21856745","display_name":"Realization (probability)","level":2,"score":0.6059374809265137},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.5481132864952087},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.49822998046875},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4863305687904358},{"id":"https://openalex.org/C36390408","wikidata":"https://www.wikidata.org/wiki/Q1163067","display_name":"Digital filter","level":3,"score":0.4807286262512207},{"id":"https://openalex.org/C100106864","wikidata":"https://www.wikidata.org/wiki/Q16001029","display_name":"2D Filters","level":5,"score":0.4602256417274475},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.4569646716117859},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.45308154821395874},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3888593912124634},{"id":"https://openalex.org/C106131492","wikidata":"https://www.wikidata.org/wiki/Q3072260","display_name":"Filter (signal processing)","level":2,"score":0.351131796836853},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.3041379451751709},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.2659471035003662},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.22232922911643982},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1481245458126068},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10332179069519043},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.09654304385185242},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.08152565360069275},{"id":"https://openalex.org/C31972630","wikidata":"https://www.wikidata.org/wiki/Q844240","display_name":"Computer vision","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2011.5937653","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2011.5937653","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE International Symposium of Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.41999998688697815}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1501488688","https://openalex.org/W1896044623","https://openalex.org/W1972580129","https://openalex.org/W2092797823","https://openalex.org/W2093353989","https://openalex.org/W2099652181","https://openalex.org/W2117764711","https://openalex.org/W2128723913","https://openalex.org/W2130703849","https://openalex.org/W2138879089","https://openalex.org/W2139700682","https://openalex.org/W6630102723"],"related_works":["https://openalex.org/W605224089","https://openalex.org/W1587252745","https://openalex.org/W4313296775","https://openalex.org/W2146985845","https://openalex.org/W2765889801","https://openalex.org/W2030335561","https://openalex.org/W2113093056","https://openalex.org/W2010296365","https://openalex.org/W2111853577","https://openalex.org/W2745152205"],"abstract_inverted_index":{"This":[0],"paper":[1],"investigates":[2],"the":[3,15,56,82,102,105,113,122,126],"potential":[4],"of":[5,17,59,84,117],"emerging":[6],"asynchronous":[7,43,47],"quasi":[8],"delay":[9],"insensitive":[10],"(a-QDI)":[11],"logic":[12,44,86],"devices":[13],"for":[14],"realization":[16,38,116],"high-speed":[18],"low-power":[19],"2D":[20,60,107,118],"infinite":[21],"impulse":[22],"response":[23],"digital":[24,91],"beam":[25,62],"filters.":[26],"Recently":[27],"proposed":[28,106],"raster-scanned":[29,66],"hardware":[30,109],"architectures":[31,78],"based":[32,64,124],"on":[33,65,125],"direct-form":[34,76],"I":[35,77],"and":[36],"wave-digital":[37,94],"are":[39,111],"extended":[40],"to":[41],"clock-free":[42,128],"using":[45,71],"state-of-the-art":[46],"field":[48],"programmable":[49],"gate":[50],"arrays":[51],"from":[52,81],"Achronix":[53],"Semiconductor.":[54],"For":[55],"specific":[57],"class":[58],"IIR":[61,108,119],"filters":[63,95,120],"hardware,":[67],"it":[68],"is":[69],"shown":[70],"extensive":[72],"experimental":[73],"work":[74],"that":[75],"greatly":[79],"benefit":[80],"adoption":[83],"a-QDI":[85,129],"over":[87],"standard":[88],"clocked":[89],"(synchronous)":[90],"circuits":[92,110],"while":[93],"show":[96],"no":[97],"difference":[98],"in":[99,121],"performance.":[100],"To":[101],"author's":[103],"knowledge,":[104],"currently":[112],"only":[114],"available":[115],"literature":[123],"new":[127],"paradigm.":[130]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
