{"id":"https://openalex.org/W2128788517","doi":"https://doi.org/10.1109/iscas.2011.5937564","title":"A dual-loop delay locked loop with multi digital delay lines for GHz DRAMs","display_name":"A dual-loop delay locked loop with multi digital delay lines for GHz DRAMs","publication_year":2011,"publication_date":"2011-05-01","ids":{"openalex":"https://openalex.org/W2128788517","doi":"https://doi.org/10.1109/iscas.2011.5937564","mag":"2128788517"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2011.5937564","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2011.5937564","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE International Symposium of Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5033895041","display_name":"Jinyeong Moon","orcid":"https://orcid.org/0000-0003-1331-348X"},"institutions":[{"id":"https://openalex.org/I10654025","display_name":"SK Group (United States)","ror":"https://ror.org/00qajw440","country_code":"US","type":"company","lineage":["https://openalex.org/I10654025","https://openalex.org/I134353371"]},{"id":"https://openalex.org/I134353371","display_name":"SK Group (South Korea)","ror":"https://ror.org/03696td91","country_code":"KR","type":"company","lineage":["https://openalex.org/I134353371"]}],"countries":["KR","US"],"is_corresponding":false,"raw_author_name":"Jinyeong Moon","raw_affiliation_strings":["DRAM Design Team II, Hynix Semiconductor, Inc., Icheon, South Korea","[DRAM Design Team II, Hynix Semiconductor, Inc., Icheon, South Korea]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"DRAM Design Team II, Hynix Semiconductor, Inc., Icheon, South Korea","institution_ids":["https://openalex.org/I134353371"]},{"raw_affiliation_string":"[DRAM Design Team II, Hynix Semiconductor, Inc., Icheon, South Korea]","institution_ids":["https://openalex.org/I10654025"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5000393014","display_name":"Hye-young Lee","orcid":null},"institutions":[{"id":"https://openalex.org/I10654025","display_name":"SK Group (United States)","ror":"https://ror.org/00qajw440","country_code":"US","type":"company","lineage":["https://openalex.org/I10654025","https://openalex.org/I134353371"]},{"id":"https://openalex.org/I134353371","display_name":"SK Group (South Korea)","ror":"https://ror.org/03696td91","country_code":"KR","type":"company","lineage":["https://openalex.org/I134353371"]}],"countries":["KR","US"],"is_corresponding":false,"raw_author_name":"Hye-young Lee","raw_affiliation_strings":["DRAM Design Team II, Hynix Semiconductor, Inc., Icheon, South Korea","[DRAM Design Team II, Hynix Semiconductor, Inc., Icheon, South Korea]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"DRAM Design Team II, Hynix Semiconductor, Inc., Icheon, South Korea","institution_ids":["https://openalex.org/I134353371"]},{"raw_affiliation_string":"[DRAM Design Team II, Hynix Semiconductor, Inc., Icheon, South Korea]","institution_ids":["https://openalex.org/I10654025"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.2703,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.64192531,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"313","last_page":"316"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11444","display_name":"Electromagnetic Compatibility and Noise Suppression","score":0.9972000122070312,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9930999875068665,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.929963231086731},{"id":"https://openalex.org/keywords/delay-locked-loop","display_name":"Delay-locked loop","score":0.8937261700630188},{"id":"https://openalex.org/keywords/dual-loop","display_name":"Dual loop","score":0.8647133708000183},{"id":"https://openalex.org/keywords/loop","display_name":"Loop (graph theory)","score":0.7467185854911804},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6031306385993958},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.5637253522872925},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.4923909902572632},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.468507319688797},{"id":"https://openalex.org/keywords/dual","display_name":"Dual (grammatical number)","score":0.45788824558258057},{"id":"https://openalex.org/keywords/control-theory","display_name":"Control theory (sociology)","score":0.3588828146457672},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2119886577129364},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17157310247421265},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.13711121678352356},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.07739618420600891}],"concepts":[{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.929963231086731},{"id":"https://openalex.org/C190462668","wikidata":"https://www.wikidata.org/wiki/Q492265","display_name":"Delay-locked loop","level":4,"score":0.8937261700630188},{"id":"https://openalex.org/C2779691726","wikidata":"https://www.wikidata.org/wiki/Q5310214","display_name":"Dual loop","level":3,"score":0.8647133708000183},{"id":"https://openalex.org/C184670325","wikidata":"https://www.wikidata.org/wiki/Q512604","display_name":"Loop (graph theory)","level":2,"score":0.7467185854911804},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6031306385993958},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.5637253522872925},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.4923909902572632},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.468507319688797},{"id":"https://openalex.org/C2780980858","wikidata":"https://www.wikidata.org/wiki/Q110022","display_name":"Dual (grammatical number)","level":2,"score":0.45788824558258057},{"id":"https://openalex.org/C47446073","wikidata":"https://www.wikidata.org/wiki/Q5165890","display_name":"Control theory (sociology)","level":3,"score":0.3588828146457672},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2119886577129364},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17157310247421265},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.13711121678352356},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.07739618420600891},{"id":"https://openalex.org/C2775924081","wikidata":"https://www.wikidata.org/wiki/Q55608371","display_name":"Control (management)","level":2,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C124952713","wikidata":"https://www.wikidata.org/wiki/Q8242","display_name":"Literature","level":1,"score":0.0},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2011.5937564","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2011.5937564","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE International Symposium of Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.5,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1533711155","https://openalex.org/W1545349055","https://openalex.org/W1979576312","https://openalex.org/W2023087202","https://openalex.org/W2059008798","https://openalex.org/W2102284281","https://openalex.org/W2124390946","https://openalex.org/W2138299146","https://openalex.org/W2266216550","https://openalex.org/W6632665017","https://openalex.org/W6645243705"],"related_works":["https://openalex.org/W2094329012","https://openalex.org/W1994021281","https://openalex.org/W2139484866","https://openalex.org/W2128788517","https://openalex.org/W2354050524","https://openalex.org/W1990914986","https://openalex.org/W3177439118","https://openalex.org/W2119216036","https://openalex.org/W4295813049","https://openalex.org/W2124954209"],"abstract_inverted_index":{"In":[0],"this":[1,21],"paper,":[2],"a":[3,23,37],"new":[4],"low-jitter":[5],"dual-loop":[6,38],"delay":[7,15,27,56],"locked":[8],"loop":[9,57],"(DLL)":[10],"with":[11],"multi":[12],"digitally":[13],"controlled":[14],"lines":[16],"(DCDLs)":[17],"is":[18,29],"proposed.":[19],"With":[20],"proposal,":[22],"limitation":[24],"on":[25],"unit":[26],"amount":[28],"drastically":[30],"reduced;":[31],"hence":[32],"the":[33,49,54,60,63,68],"maximum":[34],"frequency":[35],"that":[36],"DLL":[39],"supports":[40],"can":[41],"be":[42],"easily":[43],"expanded":[44],"into":[45],"GHz":[46],"range.":[47],"Also,":[48],"invalidation":[50],"system":[51],"employed":[52],"in":[53,62],"reference":[55],"helps":[58],"reduce":[59],"jitter":[61],"final":[64],"output":[65],"clock":[66],"of":[67],"DLL.":[69]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}