{"id":"https://openalex.org/W2010765825","doi":"https://doi.org/10.1109/iscas.2010.5537956","title":"Improving redundancy addition and removal using unreachable states for sequential circuits","display_name":"Improving redundancy addition and removal using unreachable states for sequential circuits","publication_year":2010,"publication_date":"2010-05-01","ids":{"openalex":"https://openalex.org/W2010765825","doi":"https://doi.org/10.1109/iscas.2010.5537956","mag":"2010765825"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2010.5537956","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2010.5537956","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of 2010 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100662947","display_name":"Xiaoqing Yang","orcid":"https://orcid.org/0000-0001-5161-1432"},"institutions":[{"id":"https://openalex.org/I177725633","display_name":"Chinese University of Hong Kong","ror":"https://ror.org/00t33hh48","country_code":"CN","type":"education","lineage":["https://openalex.org/I177725633"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Xiaoqing Yang","raw_affiliation_strings":["Department of Computer Science and Engineering, Chinese University of Hong Kong, Hong Kong, China","\u2021Department of Computer Science and Engineering, The Chinese University of Hong Kong"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Chinese University of Hong Kong, Hong Kong, China","institution_ids":["https://openalex.org/I177725633"]},{"raw_affiliation_string":"\u2021Department of Computer Science and Engineering, The Chinese University of Hong Kong","institution_ids":["https://openalex.org/I177725633"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5010400310","display_name":"Zigang Xiao","orcid":null},"institutions":[{"id":"https://openalex.org/I177725633","display_name":"Chinese University of Hong Kong","ror":"https://ror.org/00t33hh48","country_code":"CN","type":"education","lineage":["https://openalex.org/I177725633"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zigang Xiao","raw_affiliation_strings":["Department of Computer Science and Engineering, Chinese University of Hong Kong, Hong Kong, China","\u2021Department of Computer Science and Engineering, The Chinese University of Hong Kong"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Chinese University of Hong Kong, Hong Kong, China","institution_ids":["https://openalex.org/I177725633"]},{"raw_affiliation_string":"\u2021Department of Computer Science and Engineering, The Chinese University of Hong Kong","institution_ids":["https://openalex.org/I177725633"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5113653931","display_name":"Y. L. Wu","orcid":"https://orcid.org/0009-0009-5344-6165"},"institutions":[{"id":"https://openalex.org/I177725633","display_name":"Chinese University of Hong Kong","ror":"https://ror.org/00t33hh48","country_code":"CN","type":"education","lineage":["https://openalex.org/I177725633"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Y. L. Wu","raw_affiliation_strings":["Department of Computer Science and Engineering, Chinese University of Hong Kong, Hong Kong, China","\u2021Department of Computer Science and Engineering, The Chinese University of Hong Kong"],"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Chinese University of Hong Kong, Hong Kong, China","institution_ids":["https://openalex.org/I177725633"]},{"raw_affiliation_string":"\u2021Department of Computer Science and Engineering, The Chinese University of Hong Kong","institution_ids":["https://openalex.org/I177725633"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5100662947"],"corresponding_institution_ids":["https://openalex.org/I177725633"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.08962128,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"3172","last_page":"3175"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9973000288009644,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/redundancy","display_name":"Redundancy (engineering)","score":0.8559577465057373},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7144494652748108},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.6067141890525818},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.5959606170654297},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.5784839987754822},{"id":"https://openalex.org/keywords/triple-modular-redundancy","display_name":"Triple modular redundancy","score":0.4611964225769043},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.45081526041030884},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.39166131615638733},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.3808767795562744},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3773183822631836},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3504754304885864},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.32511723041534424},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1305921971797943},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.08913615345954895}],"concepts":[{"id":"https://openalex.org/C152124472","wikidata":"https://www.wikidata.org/wiki/Q1204361","display_name":"Redundancy (engineering)","level":2,"score":0.8559577465057373},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7144494652748108},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.6067141890525818},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.5959606170654297},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.5784839987754822},{"id":"https://openalex.org/C196371267","wikidata":"https://www.wikidata.org/wiki/Q3998979","display_name":"Triple modular redundancy","level":3,"score":0.4611964225769043},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.45081526041030884},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.39166131615638733},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.3808767795562744},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3773183822631836},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3504754304885864},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.32511723041534424},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1305921971797943},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.08913615345954895},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2010.5537956","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2010.5537956","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of 2010 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":25,"referenced_works":["https://openalex.org/W2000670199","https://openalex.org/W2057339729","https://openalex.org/W2098750649","https://openalex.org/W2110578688","https://openalex.org/W2110968362","https://openalex.org/W2114364095","https://openalex.org/W2119627643","https://openalex.org/W2133559461","https://openalex.org/W2140831103","https://openalex.org/W2143021572","https://openalex.org/W2159329697","https://openalex.org/W2165370339","https://openalex.org/W2168242454","https://openalex.org/W2169837676","https://openalex.org/W2170227286","https://openalex.org/W3152422203","https://openalex.org/W4232487136","https://openalex.org/W4234549046","https://openalex.org/W4238178324","https://openalex.org/W4251641645","https://openalex.org/W4255659196","https://openalex.org/W6674899214","https://openalex.org/W6677014648","https://openalex.org/W6680943654","https://openalex.org/W6685128995"],"related_works":["https://openalex.org/W29481652","https://openalex.org/W4238178324","https://openalex.org/W4248668797","https://openalex.org/W2110968362","https://openalex.org/W2161516870","https://openalex.org/W3141297747","https://openalex.org/W2106889348","https://openalex.org/W2111485030","https://openalex.org/W4390345338","https://openalex.org/W96064250"],"abstract_inverted_index":{"Redundancy":[0],"Addition":[1],"and":[2,35,57,75,104,129],"Removal":[3],"(RAR),":[4],"one":[5],"of":[6,38,94,143,151,164],"the":[7,27,72,91,97,105,123,149],"major":[8],"combinational":[9],"logic":[10],"perturbation":[11],"techniques,":[12],"has":[13],"been":[14],"shown":[15,134],"to":[16,101,115],"be":[17,51,155,159],"very":[18],"useful":[19,161],"for":[20,80,126],"many":[21],"EDA":[22],"optimization":[23],"tasks.":[24],"However,":[25],"all":[26],"currently":[28],"known":[29],"RAR":[30],"techniques":[31],"did":[32],"not":[33],"analyze":[34],"make":[36],"use":[37],"unreachable":[39,48,95,120],"states,":[40,96],"which":[41,157],"are":[42,168],"abundant":[43],"in":[44,63,148],"sequential":[45],"circuits.":[46],"These":[47],"states":[49],"can":[50,58,154],"considered":[52],"as":[53,162],"input":[54],"don't":[55],"cares":[56],"add":[59],"an":[60,138],"extra":[61],"flexibility":[62],"locating":[64,81],"alternative":[65,82,152],"wires.":[66],"In":[67],"this":[68],"paper,":[69],"we":[70],"study":[71],"fundamental":[73],"theory":[74],"propose":[76],"a":[77,140],"reasoning":[78],"scheme":[79],"wires":[83,153],"without":[84],"performing":[85],"wasteful":[86],"redundancy":[87,108],"tests.":[88],"To":[89],"explore":[90],"deeper":[92],"effect":[93],"concept":[98],"is":[99,110,133],"extended":[100],"illegal":[102,113],"assignments":[103,114],"fault":[106],"independent":[107],"identification":[109],"applied":[111],"on":[112],"find":[116],"flexibilities":[117],"introduced":[118],"by":[119],"states.":[121],"On":[122],"experiments":[124],"carried":[125],"both":[127],"MCNC":[128],"industry":[130],"benchmarks,":[131],"it":[132],"that":[135],"using":[136],"such":[137],"idea,":[139],"remarkable":[141],"increase":[142],"more":[144],"than":[145],"100%":[146],"(averagely)":[147],"number":[150],"found,":[156],"should":[158],"quite":[160],"most":[163],"today's":[165],"practical":[166],"circuits":[167],"sequential.":[169]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}