{"id":"https://openalex.org/W1980587820","doi":"https://doi.org/10.1109/iscas.2010.5537940","title":"A framework for fast design space exploration using fuzzy search for VLSI computing Architectures","display_name":"A framework for fast design space exploration using fuzzy search for VLSI computing Architectures","publication_year":2010,"publication_date":"2010-05-01","ids":{"openalex":"https://openalex.org/W1980587820","doi":"https://doi.org/10.1109/iscas.2010.5537940","mag":"1980587820"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2010.5537940","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2010.5537940","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of 2010 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111637047","display_name":"Zhipeng Zeng","orcid":null},"institutions":[{"id":"https://openalex.org/I530967","display_name":"Toronto Metropolitan University","ror":"https://ror.org/05g13zd79","country_code":"CA","type":"education","lineage":["https://openalex.org/I530967"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Zhipeng Zeng","raw_affiliation_strings":["Electrical and Computer Engineering, Ryerson University, Toronto, Canada","Electrical and Computer Engineering, Ryerson University Toronto,Canada"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering, Ryerson University, Toronto, Canada","institution_ids":["https://openalex.org/I530967"]},{"raw_affiliation_string":"Electrical and Computer Engineering, Ryerson University Toronto,Canada","institution_ids":["https://openalex.org/I530967"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101714993","display_name":"Reza Sedaghat","orcid":"https://orcid.org/0000-0003-0023-7131"},"institutions":[{"id":"https://openalex.org/I530967","display_name":"Toronto Metropolitan University","ror":"https://ror.org/05g13zd79","country_code":"CA","type":"education","lineage":["https://openalex.org/I530967"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Reza Sedaghat","raw_affiliation_strings":["Electrical and Computer Engineering, Ryerson University, Toronto, Canada","Electrical and Computer Engineering, Ryerson University Toronto,Canada"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering, Ryerson University, Toronto, Canada","institution_ids":["https://openalex.org/I530967"]},{"raw_affiliation_string":"Electrical and Computer Engineering, Ryerson University Toronto,Canada","institution_ids":["https://openalex.org/I530967"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5007001727","display_name":"Anirban Sengupta","orcid":"https://orcid.org/0000-0002-8215-7903"},"institutions":[{"id":"https://openalex.org/I530967","display_name":"Toronto Metropolitan University","ror":"https://ror.org/05g13zd79","country_code":"CA","type":"education","lineage":["https://openalex.org/I530967"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Anirban Sengupta","raw_affiliation_strings":["Electrical and Computer Engineering, Ryerson University, Toronto, Canada","Electrical and Computer Engineering, Ryerson University Toronto,Canada"],"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering, Ryerson University, Toronto, Canada","institution_ids":["https://openalex.org/I530967"]},{"raw_affiliation_string":"Electrical and Computer Engineering, Ryerson University Toronto,Canada","institution_ids":["https://openalex.org/I530967"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5111637047"],"corresponding_institution_ids":["https://openalex.org/I530967"],"apc_list":null,"apc_paid":null,"fwci":1.5161,"has_fulltext":false,"cited_by_count":24,"citation_normalized_percentile":{"value":0.83043438,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"3176","last_page":"3179"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/design-space-exploration","display_name":"Design space exploration","score":0.7584300637245178},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.7577453851699829},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.7446467280387878},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7104276418685913},{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.6839191913604736},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.569296658039093},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5553148984909058},{"id":"https://openalex.org/keywords/space-exploration","display_name":"Space exploration","score":0.48147574067115784},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.4801018536090851},{"id":"https://openalex.org/keywords/fuzzy-logic","display_name":"Fuzzy logic","score":0.43828457593917847},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4064698815345764},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3401634097099304},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.20873600244522095},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.14454638957977295},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.13827690482139587}],"concepts":[{"id":"https://openalex.org/C2776221188","wikidata":"https://www.wikidata.org/wiki/Q21072556","display_name":"Design space exploration","level":2,"score":0.7584300637245178},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.7577453851699829},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.7446467280387878},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7104276418685913},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.6839191913604736},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.569296658039093},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5553148984909058},{"id":"https://openalex.org/C104060986","wikidata":"https://www.wikidata.org/wiki/Q180046","display_name":"Space exploration","level":2,"score":0.48147574067115784},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.4801018536090851},{"id":"https://openalex.org/C58166","wikidata":"https://www.wikidata.org/wiki/Q224821","display_name":"Fuzzy logic","level":2,"score":0.43828457593917847},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4064698815345764},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3401634097099304},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.20873600244522095},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.14454638957977295},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.13827690482139587},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C146978453","wikidata":"https://www.wikidata.org/wiki/Q3798668","display_name":"Aerospace engineering","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iscas.2010.5537940","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2010.5537940","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of 2010 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.613.4072","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.613.4072","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.ee.ryerson.ca/opr/ISCAS Published 2.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W2005582489","https://openalex.org/W2073429440","https://openalex.org/W2074558871","https://openalex.org/W2102510699","https://openalex.org/W2137544620","https://openalex.org/W2168010321","https://openalex.org/W4242613073","https://openalex.org/W4249472430","https://openalex.org/W6651534275"],"related_works":["https://openalex.org/W2579738641","https://openalex.org/W4301487246","https://openalex.org/W32490004","https://openalex.org/W2145929661","https://openalex.org/W2010254791","https://openalex.org/W2168940796","https://openalex.org/W4282568311","https://openalex.org/W4313484792","https://openalex.org/W2951473296","https://openalex.org/W2883928845"],"abstract_inverted_index":{"In":[0],"High":[1],"level":[2],"Synthesis":[3],"design":[4,71],"methodology,":[5],"the":[6,11,15,46,62,77,81],"evaluation":[7],"and":[8],"selection":[9],"of":[10,49,64],"optimal":[12],"architecture":[13,44],"for":[14,33,40,45,92],"system":[16],"is":[17,57,90],"done":[18],"through":[19],"a":[20,30,97],"process":[21],"called":[22],"Design":[23],"Space":[24],"Exploration":[25],"(DSE).":[26],"This":[27],"paper":[28],"presents":[29],"novel":[31],"framework":[32],"fast":[34],"DSE":[35,89,98],"using":[36],"fuzzy":[37],"search":[38,102],"technique":[39],"optimizing":[41],"modular":[42],"computing":[43],"current":[47],"generation":[48],"multi":[50],"objective":[51],"VLSI":[52],"designs.":[53],"The":[54],"proposed":[55],"method":[56,99],"able":[58],"to":[59,67,96],"radically":[60],"reduce":[61],"number":[63],"architectural":[65],"variants":[66],"be":[68],"analyzed":[69],"during":[70,80,88],"space":[72],"exploration":[73,82],"while":[74],"simultaneously":[75],"maintaining":[76],"precision":[78],"required":[79],"process.":[83],"Significant":[84],"improvement":[85],"in":[86],"speedup":[87],"obtained":[91],"different":[93],"benchmarks,":[94],"compared":[95],"with":[100],"binary":[101],"mechanism.":[103]},"counts_by_year":[{"year":2024,"cited_by_count":2},{"year":2021,"cited_by_count":8},{"year":2019,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}
