{"id":"https://openalex.org/W2079608392","doi":"https://doi.org/10.1109/iscas.2010.5537928","title":"An all-digital PLL with a first order noise shaping Time-to-Digital Converter","display_name":"An all-digital PLL with a first order noise shaping Time-to-Digital Converter","publication_year":2010,"publication_date":"2010-05-01","ids":{"openalex":"https://openalex.org/W2079608392","doi":"https://doi.org/10.1109/iscas.2010.5537928","mag":"2079608392"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2010.5537928","is_oa":false,"landing_page_url":"http://doi.org/10.1109/iscas.2010.5537928","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of 2010 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5004318385","display_name":"Francesco Brandonisio","orcid":null},"institutions":[{"id":"https://openalex.org/I27577105","display_name":"University College Cork","ror":"https://ror.org/03265fv13","country_code":"IE","type":"education","lineage":["https://openalex.org/I27577105"]},{"id":"https://openalex.org/I181231927","display_name":"National University of Ireland","ror":"https://ror.org/00shsf120","country_code":"IE","type":"education","lineage":["https://openalex.org/I181231927"]}],"countries":["IE"],"is_corresponding":true,"raw_author_name":"Francesco Brandonisio","raw_affiliation_strings":["University College Cork and Tyndall National Institute, Cork, Ireland"],"affiliations":[{"raw_affiliation_string":"University College Cork and Tyndall National Institute, Cork, Ireland","institution_ids":["https://openalex.org/I181231927","https://openalex.org/I27577105"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5026435756","display_name":"Franco Maloberti","orcid":"https://orcid.org/0000-0001-8596-7824"},"institutions":[{"id":"https://openalex.org/I25217355","display_name":"University of Pavia","ror":"https://ror.org/00s6t1f81","country_code":"IT","type":"education","lineage":["https://openalex.org/I25217355"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"Franco Maloberti","raw_affiliation_strings":["Dept. of Electronics, University of Pavia, Pavia, Italy#TAB#"],"affiliations":[{"raw_affiliation_string":"Dept. of Electronics, University of Pavia, Pavia, Italy#TAB#","institution_ids":["https://openalex.org/I25217355"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5004318385"],"corresponding_institution_ids":["https://openalex.org/I181231927","https://openalex.org/I27577105"],"apc_list":null,"apc_paid":null,"fwci":1.1546,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.81057618,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"241","last_page":"244"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9969000220298767,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11444","display_name":"Electromagnetic Compatibility and Noise Suppression","score":0.9951000213623047,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/ring-oscillator","display_name":"Ring oscillator","score":0.8277292251586914},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.7469481229782104},{"id":"https://openalex.org/keywords/time-to-digital-converter","display_name":"Time-to-digital converter","score":0.6628785133361816},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5936180353164673},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.569200336933136},{"id":"https://openalex.org/keywords/verilog","display_name":"Verilog","score":0.5532436370849609},{"id":"https://openalex.org/keywords/noise","display_name":"Noise (video)","score":0.5334357023239136},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.49643832445144653},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.42548471689224243},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.24829328060150146},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21722158789634705},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.1838662028312683},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.17869064211845398},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.07777410745620728}],"concepts":[{"id":"https://openalex.org/C104111718","wikidata":"https://www.wikidata.org/wiki/Q2153973","display_name":"Ring oscillator","level":3,"score":0.8277292251586914},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.7469481229782104},{"id":"https://openalex.org/C99594498","wikidata":"https://www.wikidata.org/wiki/Q2434524","display_name":"Time-to-digital converter","level":4,"score":0.6628785133361816},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5936180353164673},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.569200336933136},{"id":"https://openalex.org/C2779030575","wikidata":"https://www.wikidata.org/wiki/Q827773","display_name":"Verilog","level":3,"score":0.5532436370849609},{"id":"https://openalex.org/C99498987","wikidata":"https://www.wikidata.org/wiki/Q2210247","display_name":"Noise (video)","level":3,"score":0.5334357023239136},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.49643832445144653},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.42548471689224243},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.24829328060150146},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21722158789634705},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.1838662028312683},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.17869064211845398},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.07777410745620728},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.0},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2010.5537928","is_oa":false,"landing_page_url":"http://doi.org/10.1109/iscas.2010.5537928","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of 2010 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6200000047683716,"display_name":"Sustainable cities and communities","id":"https://metadata.un.org/sdg/11"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320320847","display_name":"Science Foundation Ireland","ror":"https://ror.org/0271asj38"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W146784561","https://openalex.org/W1264452269","https://openalex.org/W1775840686","https://openalex.org/W2084208742","https://openalex.org/W2113319198","https://openalex.org/W2117325338","https://openalex.org/W2128282260","https://openalex.org/W2160412553","https://openalex.org/W2177833654","https://openalex.org/W6605992514"],"related_works":["https://openalex.org/W1994021281","https://openalex.org/W2139484866","https://openalex.org/W1589093285","https://openalex.org/W3176961938","https://openalex.org/W3158414702","https://openalex.org/W2992346850","https://openalex.org/W145049781","https://openalex.org/W2147061220","https://openalex.org/W2134779194","https://openalex.org/W2129773844"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"an":[3],"All":[4],"Digital":[5],"PLL":[6],"(ADPLL)":[7],"based":[8,49],"on":[9],"a":[10,25],"first":[11],"order":[12],"noise":[13],"shaping":[14],"Time-to-Digital":[15],"Converter":[16],"(TDC).":[17],"The":[18,34],"architectures":[19],"of":[20,36,44,55,61,77,88],"two":[21],"state-of-art":[22,26],"ADPLLs":[23],"and":[24,66],"Gated":[27],"Ring":[28],"Oscillator":[29,48],"(GRO)":[30],"TDC":[31,39,50,82],"are":[32,70,84],"described.":[33],"architecture":[35],"the":[37,45,62,74,81],"GRO":[38,68],"is":[40],"compared":[41,85],"with":[42],"that":[43],"proposed":[46],"Local":[47],"(LO":[51],"TDC)":[52],"in":[53],"terms":[54],"spectral":[56],"performance.":[57],"Behavioral":[58],"Verilog-AMS":[59,75],"models":[60,76],"LO,":[63,65],"exact":[64,67],"TDCs":[69],"described":[71],"briefly.":[72],"Finally,":[73],"three":[78],"ADPLLs,":[79],"including":[80],"models,":[83],"by":[86],"means":[87],"simulations.":[89]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
