{"id":"https://openalex.org/W2017916652","doi":"https://doi.org/10.1109/iscas.2010.5537884","title":"Linearity enhancement in Digital-to-Analog Converters using a modified decoding architecture","display_name":"Linearity enhancement in Digital-to-Analog Converters using a modified decoding architecture","publication_year":2010,"publication_date":"2010-05-01","ids":{"openalex":"https://openalex.org/W2017916652","doi":"https://doi.org/10.1109/iscas.2010.5537884","mag":"2017916652"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2010.5537884","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2010.5537884","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of 2010 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5050130075","display_name":"S. Moslem Hokmabadi","orcid":null},"institutions":[{"id":"https://openalex.org/I86958956","display_name":"Ferdowsi University of Mashhad","ror":"https://ror.org/00g6ka752","country_code":"IR","type":"education","lineage":["https://openalex.org/I86958956"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"S. Moslem Hokmabadi","raw_affiliation_strings":["Integrated Systems Laboratory, EE Department, Ferdowsi University of Mashhad, Mashhad, Iran","Integrated Systems Lab., EE Department, Ferdowsi University of Mashhad, Mashhad, I.R. Iran"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Integrated Systems Laboratory, EE Department, Ferdowsi University of Mashhad, Mashhad, Iran","institution_ids":["https://openalex.org/I86958956"]},{"raw_affiliation_string":"Integrated Systems Lab., EE Department, Ferdowsi University of Mashhad, Mashhad, I.R. Iran","institution_ids":["https://openalex.org/I86958956"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101600647","display_name":"Reza Lotfi","orcid":"https://orcid.org/0000-0002-8422-1809"},"institutions":[{"id":"https://openalex.org/I86958956","display_name":"Ferdowsi University of Mashhad","ror":"https://ror.org/00g6ka752","country_code":"IR","type":"education","lineage":["https://openalex.org/I86958956"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"Reza Lotfi","raw_affiliation_strings":["Integrated Systems Laboratory, EE Department, Ferdowsi University of Mashhad, Mashhad, Iran","Integrated Systems Lab., EE Department, Ferdowsi University of Mashhad, Mashhad, I.R. Iran"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Integrated Systems Laboratory, EE Department, Ferdowsi University of Mashhad, Mashhad, Iran","institution_ids":["https://openalex.org/I86958956"]},{"raw_affiliation_string":"Integrated Systems Lab., EE Department, Ferdowsi University of Mashhad, Mashhad, I.R. Iran","institution_ids":["https://openalex.org/I86958956"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I86958956"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.14163959,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"55","issue":null,"first_page":"3361","last_page":"3364"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12564","display_name":"Sensor Technology and Measurement Systems","score":0.996999979019165,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9951000213623047,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/unary-operation","display_name":"Unary operation","score":0.731577455997467},{"id":"https://openalex.org/keywords/multiplexer","display_name":"Multiplexer","score":0.6959278583526611},{"id":"https://openalex.org/keywords/spurious-free-dynamic-range","display_name":"Spurious-free dynamic range","score":0.6710776686668396},{"id":"https://openalex.org/keywords/linearity","display_name":"Linearity","score":0.6664488315582275},{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.5869041681289673},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5603919625282288},{"id":"https://openalex.org/keywords/converters","display_name":"Converters","score":0.5533450245857239},{"id":"https://openalex.org/keywords/binary-number","display_name":"Binary number","score":0.5254879593849182},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.523430585861206},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4247787296772003},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2864789366722107},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.25821179151535034},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2228589951992035},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.21593257784843445},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.18142986297607422},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.16142764687538147},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.14293107390403748},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09807604551315308}],"concepts":[{"id":"https://openalex.org/C78023250","wikidata":"https://www.wikidata.org/wiki/Q657596","display_name":"Unary operation","level":2,"score":0.731577455997467},{"id":"https://openalex.org/C70970002","wikidata":"https://www.wikidata.org/wiki/Q189434","display_name":"Multiplexer","level":3,"score":0.6959278583526611},{"id":"https://openalex.org/C119293636","wikidata":"https://www.wikidata.org/wiki/Q657480","display_name":"Spurious-free dynamic range","level":3,"score":0.6710776686668396},{"id":"https://openalex.org/C77170095","wikidata":"https://www.wikidata.org/wiki/Q1753188","display_name":"Linearity","level":2,"score":0.6664488315582275},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.5869041681289673},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5603919625282288},{"id":"https://openalex.org/C2778422915","wikidata":"https://www.wikidata.org/wiki/Q10302051","display_name":"Converters","level":3,"score":0.5533450245857239},{"id":"https://openalex.org/C48372109","wikidata":"https://www.wikidata.org/wiki/Q3913","display_name":"Binary number","level":2,"score":0.5254879593849182},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.523430585861206},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4247787296772003},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2864789366722107},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.25821179151535034},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2228589951992035},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.21593257784843445},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.18142986297607422},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.16142764687538147},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.14293107390403748},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09807604551315308},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2010.5537884","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2010.5537884","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of 2010 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1484866567","https://openalex.org/W2002579833","https://openalex.org/W2042056852","https://openalex.org/W2097892834","https://openalex.org/W2098920926","https://openalex.org/W2126860636","https://openalex.org/W2140823559","https://openalex.org/W2165630788","https://openalex.org/W2169607517","https://openalex.org/W2572971143","https://openalex.org/W6661114264","https://openalex.org/W6731652433"],"related_works":["https://openalex.org/W2552855081","https://openalex.org/W2888918612","https://openalex.org/W2098920926","https://openalex.org/W2166285859","https://openalex.org/W2143048169","https://openalex.org/W3148597776","https://openalex.org/W2029461083","https://openalex.org/W3032791449","https://openalex.org/W2953726986","https://openalex.org/W2354856110"],"abstract_inverted_index":{"In":[0,16],"this":[1,17],"paper,":[2],"a":[3,124],"novel":[4],"architecture":[5,69,119],"for":[6,108],"implementation":[7],"of":[8,21,64,122,142,152],"segmented":[9],"Digital-to-Analog":[10],"Converters":[11],"(DACs)":[12],"has":[13,24,113],"been":[14,25],"proposed.":[15],"architecture,":[18],"the":[19,49,60,77,81,90,117,120,136,140,143,150,153,157],"array":[20,155],"unit":[22],"elements":[23,145],"divided":[26],"into":[27],"four":[28],"similar":[29],"sub-arrays":[30,50,65],"and":[31,89,156],"binary":[32],"to":[33,48,59,72,79],"thermometry":[34],"conversion":[35],"is":[36,66,128],"performed":[37],"in":[38,51,70,86,116],"three":[39],"control":[40,44],"levels.":[41],"The":[42],"proposed":[43,118],"levels":[45],"are":[46],"connected":[47],"different":[52,55,87],"sequences,":[53],"thus":[54],"analog":[56],"outputs":[57],"according":[58],"random":[61],"mismatch":[62,141],"distribution":[63],"achieved.":[67],"This":[68],"addition":[71],"an":[73,109],"extra":[74],"multiplexer":[75],"provides":[76],"possibility":[78],"test":[80],"chip":[82,159],"after":[83],"its":[84],"fabrication":[85],"sequences":[88],"most":[91],"linear":[92,126,138],"one":[93],"based":[94],"on":[95],"static":[96],"linearity":[97],"metric":[98],"(INL-Yield)":[99],"or":[100],"dynamic":[101],"performance":[102],"(SFDR)":[103],"be":[104,147,161],"selected.":[105],"Monte-Carlo":[106],"simulations":[107],"8-bit":[110],"unary":[111,144,154],"DAC":[112,127],"shown":[114],"that":[115],"probability":[121],"achieving":[123],"more":[125,130],"much":[129],"than":[131],"conventional":[132],"one.":[133],"Hence,":[134],"preserving":[135],"required":[137],"output,":[139],"could":[146,160],"increased":[148],"i.e.":[149],"area":[151],"whole":[158],"decreased.":[162]},"counts_by_year":[],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
