{"id":"https://openalex.org/W1989506555","doi":"https://doi.org/10.1109/iscas.2010.5537838","title":"A low-power cell-based-design multi-port register file in 65nm CMOS technology","display_name":"A low-power cell-based-design multi-port register file in 65nm CMOS technology","publication_year":2010,"publication_date":"2010-05-01","ids":{"openalex":"https://openalex.org/W1989506555","doi":"https://doi.org/10.1109/iscas.2010.5537838","mag":"1989506555"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2010.5537838","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2010.5537838","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of 2010 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5113566749","display_name":"Johannes Uhlig","orcid":null},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Johannes Uhlig","raw_affiliation_strings":["Department of Electrical Engineering, Technische Universit\u00e4t, Dresden, Dresden, Germany","Department of Electrical Engineering, Technische Universit\u00e4t Dresden, Dresden, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Technische Universit\u00e4t, Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]},{"raw_affiliation_string":"Department of Electrical Engineering, Technische Universit\u00e4t Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5050298468","display_name":"Sebastian H\u00f6ppner","orcid":"https://orcid.org/0000-0002-9938-2736"},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Sebastian Hoppner","raw_affiliation_strings":["Department of Electrical Engineering, Technische Universit\u00e4t, Dresden, Dresden, Germany","Department of Electrical Engineering, Technische Universit\u00e4t Dresden, Dresden, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Technische Universit\u00e4t, Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]},{"raw_affiliation_string":"Department of Electrical Engineering, Technische Universit\u00e4t Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059380044","display_name":"Georg Ellguth","orcid":null},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Georg Ellguth","raw_affiliation_strings":["Department of Electrical Engineering, Technische Universit\u00e4t, Dresden, Dresden, Germany","Department of Electrical Engineering, Technische Universit\u00e4t Dresden, Dresden, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Technische Universit\u00e4t, Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]},{"raw_affiliation_string":"Department of Electrical Engineering, Technische Universit\u00e4t Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110046407","display_name":"Ren\u00e9 Sch\u00fcffny","orcid":null},"institutions":[{"id":"https://openalex.org/I78650965","display_name":"Technische Universit\u00e4t Dresden","ror":"https://ror.org/042aqky30","country_code":"DE","type":"education","lineage":["https://openalex.org/I78650965"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Rene Schuffny","raw_affiliation_strings":["Department of Electrical Engineering, Technische Universit\u00e4t, Dresden, Dresden, Germany","Department of Electrical Engineering, Technische Universit\u00e4t Dresden, Dresden, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Technische Universit\u00e4t, Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]},{"raw_affiliation_string":"Department of Electrical Engineering, Technische Universit\u00e4t Dresden, Dresden, Germany","institution_ids":["https://openalex.org/I78650965"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I78650965"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"313","last_page":"316"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/register-file","display_name":"Register file","score":0.8786929249763489},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7199890613555908},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.6891364455223083},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6311383843421936},{"id":"https://openalex.org/keywords/port","display_name":"Port (circuit theory)","score":0.5538573861122131},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.5062424540519714},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.48478835821151733},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4420641362667084},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3991243839263916},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.33093178272247314},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.2989290952682495},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2630492150783539},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.10428369045257568}],"concepts":[{"id":"https://openalex.org/C117280010","wikidata":"https://www.wikidata.org/wiki/Q180944","display_name":"Register file","level":3,"score":0.8786929249763489},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7199890613555908},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.6891364455223083},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6311383843421936},{"id":"https://openalex.org/C32802771","wikidata":"https://www.wikidata.org/wiki/Q2443617","display_name":"Port (circuit theory)","level":2,"score":0.5538573861122131},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.5062424540519714},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.48478835821151733},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4420641362667084},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3991243839263916},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.33093178272247314},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.2989290952682495},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2630492150783539},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.10428369045257568},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2010.5537838","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2010.5537838","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of 2010 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6899999976158142,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1482224770","https://openalex.org/W1510875322","https://openalex.org/W1559448125","https://openalex.org/W2032709177","https://openalex.org/W2096335660","https://openalex.org/W2105402750","https://openalex.org/W2131500512","https://openalex.org/W2133717366","https://openalex.org/W2170329515","https://openalex.org/W2544297351"],"related_works":["https://openalex.org/W4253195573","https://openalex.org/W2020934033","https://openalex.org/W2070694218","https://openalex.org/W63276784","https://openalex.org/W2532822217","https://openalex.org/W3011978806","https://openalex.org/W2059530328","https://openalex.org/W2156446048","https://openalex.org/W1989506555","https://openalex.org/W2163890360"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"the":[3,33],"design":[4,26,61],"of":[5,69,73],"a":[6,59,77],"register":[7],"file":[8],"with":[9],"4":[10],"write":[11],"and":[12,44,53,71,89],"6":[13],"read":[14],"ports":[15],"for":[16,55],"an":[17],"SDR":[18],"multiprocessor":[19],"in":[20,31],"65nm":[21],"CMOS":[22],"technology.":[23],"A":[24],"cell-based":[25],"(CBD)":[27],"methodology":[28],"is":[29,35,48,84,94],"employed":[30],"which":[32,93],"circuit":[34],"partitioned":[36],"into":[37,58],"complex":[38],"sub-cells,":[39],"optimized":[40],"on":[41],"transistor":[42],"level":[43],"layout.":[45],"Each":[46],"cell":[47],"completely":[49],"characterized":[50],"concerning":[51],"timing":[52],"power":[54,70,83],"seamless":[56],"integration":[57],"semi-custom":[60,79],"flow.":[62],"The":[63,81],"CBD":[64],"implementation":[65],"shows":[66],"30%":[67],"savings":[68],"40%":[72],"area":[74],"compared":[75],"to":[76,96],"conventional":[78],"solution.":[80],"average":[82],"2.7mW":[85],"from":[86],"1.0V":[87],"supply":[88],"300MHz":[90],"operating":[91],"frequency":[92],"superior":[95],"previously":[97],"published":[98],"designs.":[99]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
