{"id":"https://openalex.org/W2079097625","doi":"https://doi.org/10.1109/iscas.2010.5537742","title":"VLSI implementation of a low-complexity LLL lattice reduction algorithm for MIMO detection","display_name":"VLSI implementation of a low-complexity LLL lattice reduction algorithm for MIMO detection","publication_year":2010,"publication_date":"2010-05-01","ids":{"openalex":"https://openalex.org/W2079097625","doi":"https://doi.org/10.1109/iscas.2010.5537742","mag":"2079097625"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2010.5537742","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2010.5537742","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of 2010 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://infoscience.epfl.ch/record/166573","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5055941310","display_name":"Lukas Bruderer","orcid":null},"institutions":[{"id":"https://openalex.org/I35440088","display_name":"ETH Zurich","ror":"https://ror.org/05a28rw58","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I35440088"]}],"countries":["CH"],"is_corresponding":true,"raw_author_name":"L. Bruderer","raw_affiliation_strings":["Integrated Systems Laboratory, ETH Zurich, Zurich, Switzerland","Integrated Systems Laboratory, ETH Zurich, 8092 Zurich, Switzerland"],"affiliations":[{"raw_affiliation_string":"Integrated Systems Laboratory, ETH Zurich, Zurich, Switzerland","institution_ids":["https://openalex.org/I35440088"]},{"raw_affiliation_string":"Integrated Systems Laboratory, ETH Zurich, 8092 Zurich, Switzerland","institution_ids":["https://openalex.org/I35440088"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5083617223","display_name":"Christoph Studer","orcid":"https://orcid.org/0000-0001-8950-6267"},"institutions":[{"id":"https://openalex.org/I35440088","display_name":"ETH Zurich","ror":"https://ror.org/05a28rw58","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I35440088"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"C. Studer","raw_affiliation_strings":["Communication Technology Laboratory, ETH Zurich, Zurich, Switzerland","Communication Technology Laboratory ETH Zurich, 8092 Zurich, Switzerland"],"affiliations":[{"raw_affiliation_string":"Communication Technology Laboratory, ETH Zurich, Zurich, Switzerland","institution_ids":["https://openalex.org/I35440088"]},{"raw_affiliation_string":"Communication Technology Laboratory ETH Zurich, 8092 Zurich, Switzerland","institution_ids":["https://openalex.org/I35440088"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5091839299","display_name":"M. Wenk","orcid":null},"institutions":[{"id":"https://openalex.org/I35440088","display_name":"ETH Zurich","ror":"https://ror.org/05a28rw58","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I35440088"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"M. Wenk","raw_affiliation_strings":["Integrated Systems Laboratory, ETH Zurich, Zurich, Switzerland","Integrated Systems Laboratory, ETH Zurich, 8092 Zurich, Switzerland"],"affiliations":[{"raw_affiliation_string":"Integrated Systems Laboratory, ETH Zurich, Zurich, Switzerland","institution_ids":["https://openalex.org/I35440088"]},{"raw_affiliation_string":"Integrated Systems Laboratory, ETH Zurich, 8092 Zurich, Switzerland","institution_ids":["https://openalex.org/I35440088"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5041671661","display_name":"Dominik Seethaler","orcid":null},"institutions":[{"id":"https://openalex.org/I35440088","display_name":"ETH Zurich","ror":"https://ror.org/05a28rw58","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I35440088"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"D. Seethaler","raw_affiliation_strings":["Communication Technology Laboratory, ETH Zurich, Zurich, Switzerland","Communication Technology Laboratory ETH Zurich, 8092 Zurich, Switzerland"],"affiliations":[{"raw_affiliation_string":"Communication Technology Laboratory, ETH Zurich, Zurich, Switzerland","institution_ids":["https://openalex.org/I35440088"]},{"raw_affiliation_string":"Communication Technology Laboratory ETH Zurich, 8092 Zurich, Switzerland","institution_ids":["https://openalex.org/I35440088"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5059133771","display_name":"Andreas Burg","orcid":"https://orcid.org/0000-0002-7270-5558"},"institutions":[{"id":"https://openalex.org/I35440088","display_name":"ETH Zurich","ror":"https://ror.org/05a28rw58","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I35440088"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"A. Burg","raw_affiliation_strings":["Integrated Systems Laboratory, ETH Zurich, Zurich, Switzerland","Integrated Systems Laboratory, ETH Zurich, 8092 Zurich, Switzerland"],"affiliations":[{"raw_affiliation_string":"Integrated Systems Laboratory, ETH Zurich, Zurich, Switzerland","institution_ids":["https://openalex.org/I35440088"]},{"raw_affiliation_string":"Integrated Systems Laboratory, ETH Zurich, 8092 Zurich, Switzerland","institution_ids":["https://openalex.org/I35440088"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5055941310"],"corresponding_institution_ids":["https://openalex.org/I35440088"],"apc_list":null,"apc_paid":null,"fwci":4.115,"has_fulltext":false,"cited_by_count":28,"citation_normalized_percentile":{"value":0.94139342,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"3745","last_page":"3748"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10125","display_name":"Advanced Wireless Communication Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10125","display_name":"Advanced Wireless Communication Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11130","display_name":"Coding theory and cryptography","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10796","display_name":"Cooperative Communication and Network Coding","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/lattice-reduction","display_name":"Lattice reduction","score":0.8668896555900574},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.7634822130203247},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7146064639091492},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.7134088277816772},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7058147192001343},{"id":"https://openalex.org/keywords/mimo","display_name":"MIMO","score":0.6452827453613281},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6136130690574646},{"id":"https://openalex.org/keywords/single-antenna-interference-cancellation","display_name":"Single antenna interference cancellation","score":0.547863781452179},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.5330300331115723},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.5318512320518494},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.49060359597206116},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.43819886445999146},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.4291800856590271},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3817538022994995},{"id":"https://openalex.org/keywords/wireless","display_name":"Wireless","score":0.35535728931427},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.34426021575927734},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3367944359779358},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3336758017539978},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.24251189827919006},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.14841455221176147},{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.1367877721786499},{"id":"https://openalex.org/keywords/channel","display_name":"Channel (broadcasting)","score":0.12506559491157532},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12302175164222717},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07290121912956238}],"concepts":[{"id":"https://openalex.org/C44274781","wikidata":"https://www.wikidata.org/wiki/Q6497132","display_name":"Lattice reduction","level":4,"score":0.8668896555900574},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.7634822130203247},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7146064639091492},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.7134088277816772},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7058147192001343},{"id":"https://openalex.org/C207987634","wikidata":"https://www.wikidata.org/wiki/Q176862","display_name":"MIMO","level":3,"score":0.6452827453613281},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6136130690574646},{"id":"https://openalex.org/C83204339","wikidata":"https://www.wikidata.org/wiki/Q7523915","display_name":"Single antenna interference cancellation","level":3,"score":0.547863781452179},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.5330300331115723},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.5318512320518494},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.49060359597206116},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.43819886445999146},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.4291800856590271},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3817538022994995},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.35535728931427},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.34426021575927734},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3367944359779358},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3336758017539978},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.24251189827919006},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.14841455221176147},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.1367877721786499},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.12506559491157532},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12302175164222717},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07290121912956238},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iscas.2010.5537742","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2010.5537742","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of 2010 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},{"id":"pmh:oai:infoscience.epfl.ch:166573","is_oa":true,"landing_page_url":"http://infoscience.epfl.ch/record/166573","pdf_url":null,"source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Text"}],"best_oa_location":{"id":"pmh:oai:infoscience.epfl.ch:166573","is_oa":true,"landing_page_url":"http://infoscience.epfl.ch/record/166573","pdf_url":null,"source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Text"},"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W1537698448","https://openalex.org/W1542869039","https://openalex.org/W1996359168","https://openalex.org/W2013393794","https://openalex.org/W2100880214","https://openalex.org/W2122048826","https://openalex.org/W2123218077","https://openalex.org/W2129807578","https://openalex.org/W2134230263","https://openalex.org/W2138252828","https://openalex.org/W2141040012","https://openalex.org/W2147842066","https://openalex.org/W2158900434","https://openalex.org/W2163903175","https://openalex.org/W2169390701","https://openalex.org/W2808237721","https://openalex.org/W2912759893","https://openalex.org/W4299081237","https://openalex.org/W4302606928","https://openalex.org/W6632495270","https://openalex.org/W6681703196"],"related_works":["https://openalex.org/W2042331445","https://openalex.org/W2134230263","https://openalex.org/W2129251126","https://openalex.org/W2950467063","https://openalex.org/W2079759874","https://openalex.org/W2806730547","https://openalex.org/W2158041922","https://openalex.org/W2078923360","https://openalex.org/W2289024301","https://openalex.org/W2493443755"],"abstract_inverted_index":{"Lattice-reduction":[0],"(LR)-aided":[1],"successive":[2],"interference":[3],"cancellation":[4],"(SIC)":[5],"is":[6],"able":[7],"to":[8],"achieve":[9],"close-to":[10],"optimum":[11],"error-rate":[12],"performance":[13],"for":[14,39,83],"data":[15,41],"detection":[16],"in":[17,70],"multiple-input":[18],"multiple-output":[19],"(MIMO)":[20],"wireless":[21],"communication":[22],"systems.":[23],"In":[24],"this":[25,44],"work,":[26],"we":[27,46],"propose":[28],"a":[29],"hardware-efficient":[30],"VLSI":[31],"architecture":[32],"of":[33,72],"the":[34],"Lenstra-Lenstra-Lov\u00e1sz":[35],"(LLL)":[36],"LR":[37,68],"algorithm":[38],"SIC-based":[40],"detection.":[42],"For":[43],"purpose,":[45],"introduce":[47],"various":[48],"algorithmic":[49],"modifications":[50],"that":[51,63],"enable":[52],"an":[53],"efficient":[54],"hardware":[55],"implementation.":[56],"Comparisons":[57],"with":[58],"existing":[59],"FPGA":[60],"implementations":[61,69],"show":[62],"our":[64],"design":[65],"outperforms":[66],"state-of-the-art":[67],"terms":[71],"hardware-efficiency":[73],"and":[74],"throughput.":[75],"We":[76],"finally":[77],"provide":[78],"reference":[79],"ASIC":[80],"implementation":[81],"results":[82],"130nm":[84],"CMOS":[85],"technology.":[86]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":4},{"year":2014,"cited_by_count":4},{"year":2013,"cited_by_count":4},{"year":2012,"cited_by_count":3}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}