{"id":"https://openalex.org/W1983432391","doi":"https://doi.org/10.1109/iscas.2010.5537703","title":"A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface","display_name":"A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface","publication_year":2010,"publication_date":"2010-05-01","ids":{"openalex":"https://openalex.org/W1983432391","doi":"https://doi.org/10.1109/iscas.2010.5537703","mag":"1983432391"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2010.5537703","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2010.5537703","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of 2010 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100334311","display_name":"Hyun-Woo Lee","orcid":"https://orcid.org/0000-0001-9484-8456"},"institutions":[{"id":"https://openalex.org/I197347611","display_name":"Korea University","ror":"https://ror.org/047dqcg40","country_code":"KR","type":"education","lineage":["https://openalex.org/I197347611"]}],"countries":["KR"],"is_corresponding":true,"raw_author_name":"Hyun-Woo Lee","raw_affiliation_strings":["DRAM Design Team, Hynix Semiconductor, Inc., Icheon, Kyunggi, South Korea","Department of Nano-Semiconductor engineering, Korea University, Seoul, South Korea"],"affiliations":[{"raw_affiliation_string":"DRAM Design Team, Hynix Semiconductor, Inc., Icheon, Kyunggi, South Korea","institution_ids":[]},{"raw_affiliation_string":"Department of Nano-Semiconductor engineering, Korea University, Seoul, South Korea","institution_ids":["https://openalex.org/I197347611"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101404638","display_name":"Yong\u2010Hoon Kim","orcid":"https://orcid.org/0000-0003-0057-1893"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Yong-Hoon Kim","raw_affiliation_strings":["DRAM Design Team, Hynix Semiconductor, Inc., Icheon, Kyunggi, South Korea"],"affiliations":[{"raw_affiliation_string":"DRAM Design Team, Hynix Semiconductor, Inc., Icheon, Kyunggi, South Korea","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100993148","display_name":"Won-Joo Yun","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Won-Joo Yun","raw_affiliation_strings":["DRAM Design Team, Hynix Semiconductor, Inc., Icheon, Kyunggi, South Korea"],"affiliations":[{"raw_affiliation_string":"DRAM Design Team, Hynix Semiconductor, Inc., Icheon, Kyunggi, South Korea","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100734500","display_name":"Eun Young Park","orcid":"https://orcid.org/0000-0003-2430-5282"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Eun Young Park","raw_affiliation_strings":["DRAM Design Team, Hynix Semiconductor, Inc., Icheon, Kyunggi, South Korea"],"affiliations":[{"raw_affiliation_string":"DRAM Design Team, Hynix Semiconductor, Inc., Icheon, Kyunggi, South Korea","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5062807530","display_name":"Kang Youl Lee","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Kang Youl Lee","raw_affiliation_strings":["DRAM Design Team, Hynix Semiconductor, Inc., Icheon, Kyunggi, South Korea"],"affiliations":[{"raw_affiliation_string":"DRAM Design Team, Hynix Semiconductor, Inc., Icheon, Kyunggi, South Korea","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5056962236","display_name":"Jaeil Kim","orcid":"https://orcid.org/0000-0002-9799-1773"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Jaeil Kim","raw_affiliation_strings":["DRAM Design Team, Hynix Semiconductor, Inc., Icheon, Kyunggi, South Korea"],"affiliations":[{"raw_affiliation_string":"DRAM Design Team, Hynix Semiconductor, Inc., Icheon, Kyunggi, South Korea","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101504955","display_name":"Kwang Hyun Kim","orcid":"https://orcid.org/0000-0002-0094-5448"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Kwang Hyun Kim","raw_affiliation_strings":["DRAM Design Team, Hynix Semiconductor, Inc., Icheon, Kyunggi, South Korea"],"affiliations":[{"raw_affiliation_string":"DRAM Design Team, Hynix Semiconductor, Inc., Icheon, Kyunggi, South Korea","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5110324785","display_name":"Jong Ho Jung","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Jong Ho Jung","raw_affiliation_strings":["DRAM Design Team, Hynix Semiconductor, Inc., Icheon, Kyunggi, South Korea"],"affiliations":[{"raw_affiliation_string":"DRAM Design Team, Hynix Semiconductor, Inc., Icheon, Kyunggi, South Korea","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5046854464","display_name":"Kyung Whan Kim","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Kyung Whan Kim","raw_affiliation_strings":["DRAM Design Team, Hynix Semiconductor, Inc., Icheon, Kyunggi, South Korea"],"affiliations":[{"raw_affiliation_string":"DRAM Design Team, Hynix Semiconductor, Inc., Icheon, Kyunggi, South Korea","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5053450969","display_name":"Nam Gyu Rye","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Nam Gyu Rye","raw_affiliation_strings":["DRAM Design Team, Hynix Semiconductor, Inc., Icheon, Kyunggi, South Korea"],"affiliations":[{"raw_affiliation_string":"DRAM Design Team, Hynix Semiconductor, Inc., Icheon, Kyunggi, South Korea","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5088184288","display_name":"Kwan-Weon Kim","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Kwan-Weon Kim","raw_affiliation_strings":["DRAM Design Team, Hynix Semiconductor, Inc., Icheon, Kyunggi, South Korea"],"affiliations":[{"raw_affiliation_string":"DRAM Design Team, Hynix Semiconductor, Inc., Icheon, Kyunggi, South Korea","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5049311502","display_name":"Jun Hyun Chun","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Jun Hyun Chun","raw_affiliation_strings":["DRAM Design Team, Hynix Semiconductor, Inc., Icheon, Kyunggi, South Korea"],"affiliations":[{"raw_affiliation_string":"DRAM Design Team, Hynix Semiconductor, Inc., Icheon, Kyunggi, South Korea","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100777100","display_name":"Chulwoo Kim","orcid":"https://orcid.org/0000-0003-4379-7905"},"institutions":[{"id":"https://openalex.org/I197347611","display_name":"Korea University","ror":"https://ror.org/047dqcg40","country_code":"KR","type":"education","lineage":["https://openalex.org/I197347611"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Chulwoo Kim","raw_affiliation_strings":["Department of Nano-Semiconductor engineering, Korea University, Seoul, South Korea"],"affiliations":[{"raw_affiliation_string":"Department of Nano-Semiconductor engineering, Korea University, Seoul, South Korea","institution_ids":["https://openalex.org/I197347611"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031072628","display_name":"Young-Jung Choi","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Young-Jung Choi","raw_affiliation_strings":["DRAM Design Team, Hynix Semiconductor, Inc., Icheon, Kyunggi, South Korea"],"affiliations":[{"raw_affiliation_string":"DRAM Design Team, Hynix Semiconductor, Inc., Icheon, Kyunggi, South Korea","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5037950533","display_name":"Byong-Tae Chung","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Byong-Tae Chung","raw_affiliation_strings":["DRAM Design Team, Hynix Semiconductor, Inc., Icheon, Kyunggi, South Korea"],"affiliations":[{"raw_affiliation_string":"DRAM Design Team, Hynix Semiconductor, Inc., Icheon, Kyunggi, South Korea","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111887452","display_name":"Joong Sik Kih","orcid":null},"institutions":[{"id":"https://openalex.org/I4575257","display_name":"Hanyang University","ror":"https://ror.org/046865y68","country_code":"KR","type":"education","lineage":["https://openalex.org/I4575257"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Joong Sik Kih","raw_affiliation_strings":["Department of Nano-Semiconductor engineering, Hanyang University, Seoul, South Korea"],"affiliations":[{"raw_affiliation_string":"Department of Nano-Semiconductor engineering, Hanyang University, Seoul, South Korea","institution_ids":["https://openalex.org/I4575257"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":16,"corresponding_author_ids":["https://openalex.org/A5100334311"],"corresponding_institution_ids":["https://openalex.org/I197347611"],"apc_list":null,"apc_paid":null,"fwci":0.2886,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.60414971,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"3861","last_page":"3864"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.8764232397079468},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.8393418788909912},{"id":"https://openalex.org/keywords/duty-cycle","display_name":"Duty cycle","score":0.5503062605857849},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.49957799911499023},{"id":"https://openalex.org/keywords/dual-loop","display_name":"Dual loop","score":0.4870312809944153},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4815688133239746},{"id":"https://openalex.org/keywords/delay-locked-loop","display_name":"Delay-locked loop","score":0.45933830738067627},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4564180374145508},{"id":"https://openalex.org/keywords/interface","display_name":"Interface (matter)","score":0.4223836660385132},{"id":"https://openalex.org/keywords/loop","display_name":"Loop (graph theory)","score":0.40937596559524536},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.39857858419418335},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.39087244868278503},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.37173426151275635},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.30062204599380493},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.19196709990501404},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.08988982439041138},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.074451744556427}],"concepts":[{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.8764232397079468},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.8393418788909912},{"id":"https://openalex.org/C199822604","wikidata":"https://www.wikidata.org/wiki/Q557120","display_name":"Duty cycle","level":3,"score":0.5503062605857849},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.49957799911499023},{"id":"https://openalex.org/C2779691726","wikidata":"https://www.wikidata.org/wiki/Q5310214","display_name":"Dual loop","level":3,"score":0.4870312809944153},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4815688133239746},{"id":"https://openalex.org/C190462668","wikidata":"https://www.wikidata.org/wiki/Q492265","display_name":"Delay-locked loop","level":4,"score":0.45933830738067627},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4564180374145508},{"id":"https://openalex.org/C113843644","wikidata":"https://www.wikidata.org/wiki/Q901882","display_name":"Interface (matter)","level":4,"score":0.4223836660385132},{"id":"https://openalex.org/C184670325","wikidata":"https://www.wikidata.org/wiki/Q512604","display_name":"Loop (graph theory)","level":2,"score":0.40937596559524536},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.39857858419418335},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.39087244868278503},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.37173426151275635},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.30062204599380493},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.19196709990501404},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.08988982439041138},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.074451744556427},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C129307140","wikidata":"https://www.wikidata.org/wiki/Q6795880","display_name":"Maximum bubble pressure method","level":3,"score":0.0},{"id":"https://openalex.org/C157915830","wikidata":"https://www.wikidata.org/wiki/Q2928001","display_name":"Bubble","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2010.5537703","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2010.5537703","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of 2010 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8399999737739563,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1540664825","https://openalex.org/W1576450352","https://openalex.org/W1978346157","https://openalex.org/W2061566786","https://openalex.org/W2092075230","https://openalex.org/W2101597431","https://openalex.org/W2130156225","https://openalex.org/W2133458494","https://openalex.org/W2538541815","https://openalex.org/W2546094853","https://openalex.org/W6644616491","https://openalex.org/W6673541384","https://openalex.org/W6679855229"],"related_works":["https://openalex.org/W1576183573","https://openalex.org/W2128788517","https://openalex.org/W2469331242","https://openalex.org/W2071605589","https://openalex.org/W1942384940","https://openalex.org/W2362438133","https://openalex.org/W1974775547","https://openalex.org/W1727155093","https://openalex.org/W2172050394","https://openalex.org/W1983432391"],"abstract_inverted_index":{"A":[0],"7.7mW/1.0ns/1.35V":[1],"digital":[2],"delay":[3,37,43],"locked":[4],"loop":[5],"has":[6],"been":[7],"proposed":[8,68],"in":[9,94],"this":[10],"paper.":[11],"The":[12,39,67],"dual-DLL":[13],"architecture":[14],"with":[15,101],"racing":[16],"operation":[17,24,103],"is":[18,29,46,73],"adopted":[19],"to":[20],"achieve":[21],"low":[22,26,49],"power":[23,50],"and":[25,51],"jitter,":[27],"which":[28],"primarily":[30],"caused":[31],"by":[32,75],"the":[33,36],"length":[34],"of":[35,88],"line.":[38],"merged":[40],"dual":[41],"coarse":[42],"line":[44],"(MDCDL)":[45],"employed":[47],"for":[48,61,70],"high":[52],"frequency":[53,104],"operation.":[54],"This":[55],"DLL":[56,69],"utilizes":[57],"an":[58],"OR-AND":[59],"DCC":[60],"wide":[62],"duty":[63,86],"cycle":[64],"correction":[65],"capability.":[66],"DDR3":[71],"SDRAM":[72],"fabricated":[74],"a":[76],"54nm":[77],"DRAM":[78],"process":[79],"technology.":[80],"Experimental":[81],"results":[82],"show":[83],"that":[84],"\u00b110%":[85],"error":[87],"external":[89],"clock":[90],"can":[91],"be":[92],"corrected":[93],"less":[95],"than":[96],"400":[97],"cycles":[98],"locking":[99],"time":[100],"1.0GHz":[102],"at":[105],"1.35V.":[106]},"counts_by_year":[{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
