{"id":"https://openalex.org/W2084902696","doi":"https://doi.org/10.1109/iscas.2010.5537658","title":"Minimal Logic Depth adder tree optimization for Multiple Constant Multiplication","display_name":"Minimal Logic Depth adder tree optimization for Multiple Constant Multiplication","publication_year":2010,"publication_date":"2010-05-01","ids":{"openalex":"https://openalex.org/W2084902696","doi":"https://doi.org/10.1109/iscas.2010.5537658","mag":"2084902696"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2010.5537658","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2010.5537658","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of 2010 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5022061486","display_name":"Mathias Faust","orcid":"https://orcid.org/0000-0003-2566-317X"},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Mathias Faust","raw_affiliation_strings":["Centre of High Performance Embedded Systems, Nanyang Technological University, Singapore","Centre for High Performance Embedded Systems, Nanyang Technological University, Singapore"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Centre of High Performance Embedded Systems, Nanyang Technological University, Singapore","institution_ids":["https://openalex.org/I172675005"]},{"raw_affiliation_string":"Centre for High Performance Embedded Systems, Nanyang Technological University, Singapore","institution_ids":["https://openalex.org/I172675005"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5029335324","display_name":"Chip-Hong Chang","orcid":"https://orcid.org/0000-0002-8897-6176"},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Chip-Hong Chang","raw_affiliation_strings":["Centre of High Performance Embedded Systems, Nanyang Technological University, Singapore","Centre for High Performance Embedded Systems, Nanyang Technological University, Singapore"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Centre of High Performance Embedded Systems, Nanyang Technological University, Singapore","institution_ids":["https://openalex.org/I172675005"]},{"raw_affiliation_string":"Centre for High Performance Embedded Systems, Nanyang Technological University, Singapore","institution_ids":["https://openalex.org/I172675005"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":4.4022,"has_fulltext":false,"cited_by_count":40,"citation_normalized_percentile":{"value":0.95006353,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"457","last_page":"460"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.7658461928367615},{"id":"https://openalex.org/keywords/glitch","display_name":"Glitch","score":0.7057636380195618},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.5456399321556091},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5356371402740479},{"id":"https://openalex.org/keywords/constant","display_name":"Constant (computer programming)","score":0.494184285402298},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.48278725147247314},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.46100208163261414},{"id":"https://openalex.org/keywords/critical-path-method","display_name":"Critical path method","score":0.44622865319252014},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4394257366657257},{"id":"https://openalex.org/keywords/multiplication","display_name":"Multiplication (music)","score":0.43801364302635193},{"id":"https://openalex.org/keywords/finite-impulse-response","display_name":"Finite impulse response","score":0.42657727003097534},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3814666271209717},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.3511456847190857},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.34943169355392456}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.7658461928367615},{"id":"https://openalex.org/C191287063","wikidata":"https://www.wikidata.org/wiki/Q543281","display_name":"Glitch","level":3,"score":0.7057636380195618},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.5456399321556091},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5356371402740479},{"id":"https://openalex.org/C2777027219","wikidata":"https://www.wikidata.org/wiki/Q1284190","display_name":"Constant (computer programming)","level":2,"score":0.494184285402298},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.48278725147247314},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.46100208163261414},{"id":"https://openalex.org/C115874739","wikidata":"https://www.wikidata.org/wiki/Q825377","display_name":"Critical path method","level":2,"score":0.44622865319252014},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4394257366657257},{"id":"https://openalex.org/C2780595030","wikidata":"https://www.wikidata.org/wiki/Q3860309","display_name":"Multiplication (music)","level":2,"score":0.43801364302635193},{"id":"https://openalex.org/C198386975","wikidata":"https://www.wikidata.org/wiki/Q117785","display_name":"Finite impulse response","level":2,"score":0.42657727003097534},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3814666271209717},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.3511456847190857},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.34943169355392456},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C94915269","wikidata":"https://www.wikidata.org/wiki/Q1834857","display_name":"Detector","level":2,"score":0.0},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2010.5537658","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2010.5537658","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of 2010 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1899783759","https://openalex.org/W1929845150","https://openalex.org/W1995422957","https://openalex.org/W2001254103","https://openalex.org/W2089902593","https://openalex.org/W2096479326","https://openalex.org/W2105101187","https://openalex.org/W2134918682","https://openalex.org/W2158089006","https://openalex.org/W2164469000","https://openalex.org/W2169484940","https://openalex.org/W6684171464"],"related_works":["https://openalex.org/W2142508560","https://openalex.org/W2022633778","https://openalex.org/W2746028461","https://openalex.org/W2308444316","https://openalex.org/W2799699812","https://openalex.org/W2787169372","https://openalex.org/W2155289750","https://openalex.org/W2159724425","https://openalex.org/W4231267350","https://openalex.org/W2117956479"],"abstract_inverted_index":{"Research":[0],"on":[1,72,147],"optimization":[2],"of":[3,22,94,119],"fixed":[4],"coefficient":[5],"FIR":[6],"filters":[7,132],"modeled":[8],"as":[9,40,82,84],"Multiple":[10],"Constant":[11],"Multiplication":[12],"(MCM)":[13],"has":[14,116],"been":[15],"ongoing":[16],"for":[17],"two":[18],"decades.":[19],"An":[20],"analysis":[21],"Minimal":[23],"Signed":[24],"Digit":[25],"(MSD)":[26],"reveals":[27],"that":[28,52,114],"potential":[29],"good":[30],"solutions":[31],"are":[32,42,55],"omitted":[33],"by":[34],"Common":[35],"Subexpression":[36],"Elimination":[37],"(CSE)":[38],"algorithms":[39,50,123],"they":[41],"hidden":[43],"in":[44],"the":[45,79,85,90,126,140,148],"MSD":[46],"representations.":[47],"Some":[48],"CSE":[49,122],"ensure":[51],"all":[53,131],"coefficients":[54],"implemented":[56],"at":[57],"minimal":[58,101,127],"Logic":[59],"Depth":[60],"(LD)":[61],"which":[62,106],"is":[63],"advantageous":[64],"from":[65],"power":[66,138],"saving":[67],"perspective.":[68],"Imposing":[69],"this":[70],"requirement":[71],"a":[73,100],"graph":[74],"dependant":[75],"(GD)":[76],"algorithm":[77,105],"reduces":[78],"search":[80],"space":[81],"well":[83],"runtime.":[86],"It":[87],"also":[88],"eliminates":[89],"long":[91],"critical":[92],"path":[93],"GD":[95,104,144],"algorithm.":[96],"This":[97],"paper":[98],"presents":[99],"logic":[102,128],"depth":[103],"requires":[107],"no":[108],"lookup":[109],"table.":[110],"Simulation":[111],"results":[112],"show":[113],"it":[115,134],"lower":[117],"number":[118],"adders":[120],"than":[121,139],"while":[124],"having":[125],"depth.":[129],"For":[130],"tested,":[133],"consumes":[135],"less":[136],"switching":[137],"latest":[141],"LD":[142],"constrained":[143],"methods":[145],"based":[146],"Glitch":[149,153],"Path":[150,154],"Count":[151],"and":[152],"Score":[155],"metrics.":[156]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":7},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":5},{"year":2014,"cited_by_count":7},{"year":2013,"cited_by_count":3},{"year":2012,"cited_by_count":3}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}