{"id":"https://openalex.org/W1973499252","doi":"https://doi.org/10.1109/iscas.2010.5537401","title":"Performance-driven high-level synthesis with floorplan for GDR architectures and its evaluation","display_name":"Performance-driven high-level synthesis with floorplan for GDR architectures and its evaluation","publication_year":2010,"publication_date":"2010-05-01","ids":{"openalex":"https://openalex.org/W1973499252","doi":"https://doi.org/10.1109/iscas.2010.5537401","mag":"1973499252"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2010.5537401","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2010.5537401","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of 2010 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5071147395","display_name":"Akira Ohchi","orcid":null},"institutions":[{"id":"https://openalex.org/I150744194","display_name":"Waseda University","ror":"https://ror.org/00ntfnx83","country_code":"JP","type":"education","lineage":["https://openalex.org/I150744194"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Akira Ohchi","raw_affiliation_strings":["Department of Computer Science and Engineering, Waseda University, Shinjuku, Tokyo, Japan","Department of Computer Science and Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Waseda University, Shinjuku, Tokyo, Japan","institution_ids":["https://openalex.org/I150744194"]},{"raw_affiliation_string":"Department of Computer Science and Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo, Japan","institution_ids":["https://openalex.org/I150744194"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5087516286","display_name":"Nozomu Togawa","orcid":"https://orcid.org/0000-0003-3400-3587"},"institutions":[{"id":"https://openalex.org/I150744194","display_name":"Waseda University","ror":"https://ror.org/00ntfnx83","country_code":"JP","type":"education","lineage":["https://openalex.org/I150744194"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Nozomu Togawa","raw_affiliation_strings":["Department of Computer Science and Engineering, Waseda University, Shinjuku, Tokyo, Japan","Department of Computer Science and Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Waseda University, Shinjuku, Tokyo, Japan","institution_ids":["https://openalex.org/I150744194"]},{"raw_affiliation_string":"Department of Computer Science and Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo, Japan","institution_ids":["https://openalex.org/I150744194"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061982025","display_name":"Masao Yanagisawa","orcid":"https://orcid.org/0000-0002-5168-3214"},"institutions":[{"id":"https://openalex.org/I150744194","display_name":"Waseda University","ror":"https://ror.org/00ntfnx83","country_code":"JP","type":"education","lineage":["https://openalex.org/I150744194"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Masao Yanagisawa","raw_affiliation_strings":["Department of Computer Science and Engineering, Waseda University, Shinjuku, Tokyo, Japan","Department of Computer Science and Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Waseda University, Shinjuku, Tokyo, Japan","institution_ids":["https://openalex.org/I150744194"]},{"raw_affiliation_string":"Department of Computer Science and Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo, Japan","institution_ids":["https://openalex.org/I150744194"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5109154058","display_name":"Tatsuo Ohtsuki","orcid":null},"institutions":[{"id":"https://openalex.org/I150744194","display_name":"Waseda University","ror":"https://ror.org/00ntfnx83","country_code":"JP","type":"education","lineage":["https://openalex.org/I150744194"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Tatsuo Ohtsuki","raw_affiliation_strings":["Department of Computer Science and Engineering, Waseda University, Shinjuku, Tokyo, Japan","Department of Computer Science and Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Science and Engineering, Waseda University, Shinjuku, Tokyo, Japan","institution_ids":["https://openalex.org/I150744194"]},{"raw_affiliation_string":"Department of Computer Science and Engineering, Waseda University, 3-4-1 Okubo, Shinjuku, Tokyo, Japan","institution_ids":["https://openalex.org/I150744194"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I150744194"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"921","last_page":"924"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.9524492025375366},{"id":"https://openalex.org/keywords/scheduling","display_name":"Scheduling (production processes)","score":0.6974026560783386},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6755752563476562},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.6572670936584473},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6087630391120911},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5398120284080505},{"id":"https://openalex.org/keywords/critical-path-method","display_name":"Critical path method","score":0.5296342968940735},{"id":"https://openalex.org/keywords/register-allocation","display_name":"Register allocation","score":0.527125895023346},{"id":"https://openalex.org/keywords/performance-improvement","display_name":"Performance improvement","score":0.5086835026741028},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.4338233470916748},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3790687918663025},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.29367780685424805},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.15933489799499512},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.14912530779838562},{"id":"https://openalex.org/keywords/mathematical-optimization","display_name":"Mathematical optimization","score":0.1389836072921753},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.11359775066375732},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.0697641372680664}],"concepts":[{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.9524492025375366},{"id":"https://openalex.org/C206729178","wikidata":"https://www.wikidata.org/wiki/Q2271896","display_name":"Scheduling (production processes)","level":2,"score":0.6974026560783386},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6755752563476562},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.6572670936584473},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6087630391120911},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5398120284080505},{"id":"https://openalex.org/C115874739","wikidata":"https://www.wikidata.org/wiki/Q825377","display_name":"Critical path method","level":2,"score":0.5296342968940735},{"id":"https://openalex.org/C128916667","wikidata":"https://www.wikidata.org/wiki/Q1343660","display_name":"Register allocation","level":3,"score":0.527125895023346},{"id":"https://openalex.org/C2778915421","wikidata":"https://www.wikidata.org/wiki/Q3643177","display_name":"Performance improvement","level":2,"score":0.5086835026741028},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.4338233470916748},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3790687918663025},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.29367780685424805},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.15933489799499512},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14912530779838562},{"id":"https://openalex.org/C126255220","wikidata":"https://www.wikidata.org/wiki/Q141495","display_name":"Mathematical optimization","level":1,"score":0.1389836072921753},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.11359775066375732},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0697641372680664},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.0},{"id":"https://openalex.org/C21547014","wikidata":"https://www.wikidata.org/wiki/Q1423657","display_name":"Operations management","level":1,"score":0.0},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2010.5537401","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2010.5537401","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of 2010 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W1965585119","https://openalex.org/W2105076302","https://openalex.org/W2108251415","https://openalex.org/W2114413820","https://openalex.org/W2148768450","https://openalex.org/W2153889277","https://openalex.org/W2158490957","https://openalex.org/W2161805663","https://openalex.org/W3146684470","https://openalex.org/W4234777321","https://openalex.org/W4240135979","https://openalex.org/W4255374779","https://openalex.org/W6675804706","https://openalex.org/W6676447351","https://openalex.org/W6677281017","https://openalex.org/W6682012092","https://openalex.org/W6682767452","https://openalex.org/W6683768037"],"related_works":["https://openalex.org/W3141861494","https://openalex.org/W2161004825","https://openalex.org/W2043900241","https://openalex.org/W2080729117","https://openalex.org/W1516038830","https://openalex.org/W2044534563","https://openalex.org/W2172010869","https://openalex.org/W2080804043","https://openalex.org/W1624807520","https://openalex.org/W1559659176"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"we":[3,15,63],"propose":[4],"a":[5,25,65],"high-level":[6],"synthesis":[7],"method":[8,50],"targeting":[9],"generalized":[10,66],"distributed-register":[11,67],"architecture":[12,68],"in":[13,46],"which":[14],"introduce":[16],"shared/local":[17],"registers":[18,30],"and":[19,31,34,43,58],"global/local":[20],"controllers.":[21],"Functional":[22],"units":[23,36],"on":[24,37,53],"critical":[26],"path":[27,39],"use":[28,40],"local":[29,32],"controllers":[33],"functional":[35],"non-critical":[38],"shared":[41],"register":[42],"global":[44],"controller":[45],"our":[47],"architecture.":[48],"Our":[49],"is":[51],"based":[52],"iterative":[54,61],"improvement":[55,85],"of":[56],"scheduling/binding":[57,71],"floorplanning.":[59],"Using":[60],"flow,":[62],"obtains":[64],"where":[69],"its":[70],"as":[72,74],"well":[73],"floorplanning":[75],"are":[76],"simultaneously":[77],"optimized.":[78],"Experimental":[79],"results":[80],"show":[81],"that":[82],"8.6%":[83],"performance":[84],"can":[86],"be":[87],"achieved":[88],"compared":[89],"to":[90],"the":[91],"conventional":[92],"high-performance":[93],"method.":[94]},"counts_by_year":[{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
