{"id":"https://openalex.org/W2150691261","doi":"https://doi.org/10.1109/iscas.2009.5118367","title":"Efficient test circuit to qualify logic cells","display_name":"Efficient test circuit to qualify logic cells","publication_year":2009,"publication_date":"2009-05-01","ids":{"openalex":"https://openalex.org/W2150691261","doi":"https://doi.org/10.1109/iscas.2009.5118367","mag":"2150691261"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2009.5118367","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2009.5118367","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5090563366","display_name":"Renato P. Ribas","orcid":"https://orcid.org/0000-0002-9895-7489"},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"R. P. Ribas","raw_affiliation_strings":["PGMicro-PPGC/UFRGS, Porto Alegre, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"PGMicro-PPGC/UFRGS, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5039609187","display_name":"Simone Bavaresco","orcid":null},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"S. Bavaresco","raw_affiliation_strings":["PGMicro-PPGC/UFRGS, Porto Alegre, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"PGMicro-PPGC/UFRGS, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5105973341","display_name":"Marcelo Lubaszewski","orcid":null},"institutions":[{"id":"https://openalex.org/I130442723","display_name":"Universidade Federal do Rio Grande do Sul","ror":"https://ror.org/041yk2d64","country_code":"BR","type":"education","lineage":["https://openalex.org/I130442723"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"M. Lubaszewski","raw_affiliation_strings":["PGMicro-PPGC/UFRGS, Porto Alegre, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"PGMicro-PPGC/UFRGS, Porto Alegre, Brazil","institution_ids":["https://openalex.org/I130442723"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5065397615","display_name":"Andr\u00e9 I. Reis","orcid":"https://orcid.org/0000-0002-3118-8160"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"A. I. Reis","raw_affiliation_strings":["Nangate, Inc., Sunnyvale, CA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Nangate, Inc., Sunnyvale, CA, USA","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":"31","issue":null,"first_page":"2733","last_page":"2736"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.6835736036300659},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6794828176498413},{"id":"https://openalex.org/keywords/register-transfer-level","display_name":"Register-transfer level","score":0.5340999364852905},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.527554452419281},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.5199548006057739},{"id":"https://openalex.org/keywords/test-set","display_name":"Test set","score":0.4931432604789734},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.49102354049682617},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.48920202255249023},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.46573156118392944},{"id":"https://openalex.org/keywords/simple","display_name":"Simple (philosophy)","score":0.43133506178855896},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.42590951919555664},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.3598545789718628},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3354009985923767},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.33277949690818787},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.3222949504852295},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.30595386028289795},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2346208393573761},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2111228108406067},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.11801809072494507},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.10691958665847778},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.07552856206893921}],"concepts":[{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.6835736036300659},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6794828176498413},{"id":"https://openalex.org/C34854456","wikidata":"https://www.wikidata.org/wiki/Q1484552","display_name":"Register-transfer level","level":4,"score":0.5340999364852905},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.527554452419281},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.5199548006057739},{"id":"https://openalex.org/C169903167","wikidata":"https://www.wikidata.org/wiki/Q3985153","display_name":"Test set","level":2,"score":0.4931432604789734},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.49102354049682617},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.48920202255249023},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.46573156118392944},{"id":"https://openalex.org/C2780586882","wikidata":"https://www.wikidata.org/wiki/Q7520643","display_name":"Simple (philosophy)","level":2,"score":0.43133506178855896},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.42590951919555664},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.3598545789718628},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3354009985923767},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.33277949690818787},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.3222949504852295},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.30595386028289795},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2346208393573761},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2111228108406067},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.11801809072494507},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.10691958665847778},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.07552856206893921},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/iscas.2009.5118367","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2009.5118367","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.913.381","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.913.381","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"https://www.researchgate.net/profile/Marcelo_Lubaszewski/publication/224535575_Efficient_test_circuit_to_qualify_logic_cells/links/09e415110034f695a2000000.pdf","raw_type":"text"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.918.7044","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.918.7044","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"https://www.researchgate.net/profile/Marcelo_Lubaszewski/publication/224535575_Efficient_test_circuit_to_qualify_logic_cells/links/09e415110034ec45d4000000.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8700000047683716,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1488372642","https://openalex.org/W1940169316","https://openalex.org/W2078179095","https://openalex.org/W2079808904","https://openalex.org/W2144689861","https://openalex.org/W2154665706","https://openalex.org/W2156294156","https://openalex.org/W2164178706","https://openalex.org/W2166006392","https://openalex.org/W2168812909","https://openalex.org/W2262295232","https://openalex.org/W2413518988","https://openalex.org/W6684298975","https://openalex.org/W6684511688"],"related_works":["https://openalex.org/W2373127312","https://openalex.org/W659242671","https://openalex.org/W2098419840","https://openalex.org/W2386022279","https://openalex.org/W2356714888","https://openalex.org/W2364534035","https://openalex.org/W1965949818","https://openalex.org/W2063209251","https://openalex.org/W1551512938","https://openalex.org/W2965922527"],"abstract_inverted_index":{"This":[0],"work":[1],"proposes":[2],"a":[3],"simple,":[4],"efficient":[5],"and":[6,12,26],"easy-to-use":[7],"test":[8],"circuit":[9],"for":[10],"evaluating":[11],"validating":[13],"any":[14],"set":[15],"of":[16,21,30],"logic":[17],"gates":[18],"in":[19,28],"terms":[20],"functionality,":[22],"performance,":[23],"power":[24],"consumption":[25],"impact":[27],"operation":[29],"sub-nanometer":[31],"physical":[32],"effects.":[33]},"counts_by_year":[{"year":2021,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}