{"id":"https://openalex.org/W2098316714","doi":"https://doi.org/10.1109/iscas.2009.5118261","title":"Bridging technology-CAD and design-CAD for variability aware Nano-CMOS circuits","display_name":"Bridging technology-CAD and design-CAD for variability aware Nano-CMOS circuits","publication_year":2009,"publication_date":"2009-05-01","ids":{"openalex":"https://openalex.org/W2098316714","doi":"https://doi.org/10.1109/iscas.2009.5118261","mag":"2098316714"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2009.5118261","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2009.5118261","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5108401813","display_name":"B. P. Harish","orcid":null},"institutions":[{"id":"https://openalex.org/I53465836","display_name":"Bangalore University","ror":"https://ror.org/050j2vm64","country_code":"IN","type":"education","lineage":["https://openalex.org/I53465836"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"B.P. Harish","raw_affiliation_strings":["Department of Electrical Engineering, UVCE, Bangalore University, Bangalore, India","Dept. of Electrical Engineering, UVCE, Bangalore University, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, UVCE, Bangalore University, Bangalore, India","institution_ids":["https://openalex.org/I53465836"]},{"raw_affiliation_string":"Dept. of Electrical Engineering, UVCE, Bangalore University, India","institution_ids":["https://openalex.org/I53465836"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5085866541","display_name":"Navakanta Bhat","orcid":"https://orcid.org/0000-0002-5356-5166"},"institutions":[{"id":"https://openalex.org/I59270414","display_name":"Indian Institute of Science Bangalore","ror":"https://ror.org/04dese585","country_code":"IN","type":"education","lineage":["https://openalex.org/I59270414"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Navakanta Bhat","raw_affiliation_strings":["Department of Electrical Communication Engineering, Indian Institute of Science, Bangalore, India","Dept. of Electrical Communication Eng., Indian Institute of Science, Bangalore, India#TAB#"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Communication Engineering, Indian Institute of Science, Bangalore, India","institution_ids":["https://openalex.org/I59270414"]},{"raw_affiliation_string":"Dept. of Electrical Communication Eng., Indian Institute of Science, Bangalore, India#TAB#","institution_ids":["https://openalex.org/I59270414"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101943503","display_name":"Mahesh B. Patil","orcid":"https://orcid.org/0000-0001-8766-1044"},"institutions":[{"id":"https://openalex.org/I162827531","display_name":"Indian Institute of Technology Bombay","ror":"https://ror.org/02qyf5152","country_code":"IN","type":"education","lineage":["https://openalex.org/I162827531"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Mahesh B. Patil","raw_affiliation_strings":["Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai, India","Dept. of Electrical Engineering, Indian Institute of Technology - Bombay, Mumbai, INDIA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Indian Institute of Technology Bombay, Mumbai, India","institution_ids":["https://openalex.org/I162827531"]},{"raw_affiliation_string":"Dept. of Electrical Engineering, Indian Institute of Technology - Bombay, Mumbai, INDIA","institution_ids":["https://openalex.org/I162827531"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.12803753,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"2309","last_page":"2312"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.7109311819076538},{"id":"https://openalex.org/keywords/cad","display_name":"CAD","score":0.6264320015907288},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.62114417552948},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6071885824203491},{"id":"https://openalex.org/keywords/technology-cad","display_name":"Technology CAD","score":0.6024793982505798},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.5814144611358643},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.568221390247345},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5539080500602722},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.535811722278595},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.5314155220985413},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.508454442024231},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.4624830186367035},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.453634113073349},{"id":"https://openalex.org/keywords/semiconductor-device-modeling","display_name":"Semiconductor device modeling","score":0.43389222025871277},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.43254178762435913},{"id":"https://openalex.org/keywords/bridging","display_name":"Bridging (networking)","score":0.4226028323173523},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.3207548260688782},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2762344181537628},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.21901404857635498},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1611328423023224},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.10849961638450623},{"id":"https://openalex.org/keywords/engineering-drawing","display_name":"Engineering drawing","score":0.09850886464118958}],"concepts":[{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.7109311819076538},{"id":"https://openalex.org/C194789388","wikidata":"https://www.wikidata.org/wiki/Q17855283","display_name":"CAD","level":2,"score":0.6264320015907288},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.62114417552948},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6071885824203491},{"id":"https://openalex.org/C34929307","wikidata":"https://www.wikidata.org/wiki/Q845636","display_name":"Technology CAD","level":3,"score":0.6024793982505798},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.5814144611358643},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.568221390247345},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5539080500602722},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.535811722278595},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.5314155220985413},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.508454442024231},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.4624830186367035},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.453634113073349},{"id":"https://openalex.org/C4775677","wikidata":"https://www.wikidata.org/wiki/Q7449393","display_name":"Semiconductor device modeling","level":3,"score":0.43389222025871277},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.43254178762435913},{"id":"https://openalex.org/C174348530","wikidata":"https://www.wikidata.org/wiki/Q188635","display_name":"Bridging (networking)","level":2,"score":0.4226028323173523},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.3207548260688782},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2762344181537628},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.21901404857635498},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1611328423023224},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.10849961638450623},{"id":"https://openalex.org/C199639397","wikidata":"https://www.wikidata.org/wiki/Q1788588","display_name":"Engineering drawing","level":1,"score":0.09850886464118958},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iscas.2009.5118261","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2009.5118261","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},{"id":"pmh:oai:eprints-bangaloreuniversity.in:1875","is_oa":false,"landing_page_url":"http://eprints-bangaloreuniversity.in/1875/1/Bridging%20Technology-CAD%20and%20Design-CAD%20for.pdf","pdf_url":null,"source":{"id":"https://openalex.org/S4306401173","display_name":"ePrints@Bangalore University (Bangalore University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I53465836","host_organization_name":"Bangalore University","host_organization_lineage":["https://openalex.org/I53465836"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Conference or Workshop Item"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1967665660","https://openalex.org/W2074854400","https://openalex.org/W2104135808","https://openalex.org/W2125892790","https://openalex.org/W2153299515","https://openalex.org/W2168356039","https://openalex.org/W4242857214","https://openalex.org/W4255862616"],"related_works":["https://openalex.org/W2020934033","https://openalex.org/W4253195573","https://openalex.org/W2366617252","https://openalex.org/W2017475176","https://openalex.org/W2143407223","https://openalex.org/W2721842800","https://openalex.org/W2064447053","https://openalex.org/W2092737038","https://openalex.org/W4389672975","https://openalex.org/W2013391748"],"abstract_inverted_index":{"Transistor":[0],"variability":[1,38,68,81],"has":[2,23],"emerged":[3],"as":[4,123,137],"one":[5,90,113],"of":[6,37,47,52,91,172,212],"the":[7,31,44,87,92,102,117,131,152,170,173,181,194,198,203,210,216,233],"important":[8,191],"constraints":[9],"in":[10,25,29,89,119,180,193,221,225,232],"Nano-CMOS":[11],"circuit":[12,62,120,156,195,218],"design.":[13],"The":[14,35,79,143],"ever":[15],"decreasing":[16],"device":[17,33,55,154],"feature":[18],"size":[19],"with":[20],"CMOS":[21,183],"scaling,":[22],"resulted":[24],"an":[26,190],"increasing":[27],"uncertainty":[28],"predicting":[30],"exact":[32],"behaviour.":[34],"issue":[36],"needs":[39],"to":[40,57,74,100,114,130,168,188],"be":[41,166],"addressed":[42],"across":[43],"entire":[45],"hierarchy":[46],"integrated":[48],"circuits":[49],"-":[50],"optimization":[51],"process":[53,134,230],"and":[54,63,71,83,107,127,155,177,228],"technology":[56,105],"yield":[58],"minimal":[59],"variability,":[60],"robust":[61],"system":[64],"design":[65,108,184,196],"architectures":[66],"for":[67],"aware":[69],"design,":[70],"CAD":[72,84,106],"tools":[73],"unify":[75],"these":[76],"two":[77,93],"domains.":[78,94],"traditional":[80],"modeling":[82,175],"techniques":[85],"address":[86],"problem":[88],"We":[95],"propose":[96],"a":[97,207,226],"unified":[98],"framework":[99,111],"bridge":[101],"gap":[103],"between":[104],"CAD.":[109],"This":[110,220],"enables":[112],"directly":[115],"relate":[116],"variation":[118],"metrics":[121],"such":[122,136],"speed,":[124],"static":[125],"power":[126,129],"dynamic":[128],"underlying":[132],"semiconductor":[133],"parameters":[135],"implant":[138],"dose,":[139],"annealing":[140],"temperature":[141],"etc.":[142],"proposed":[144,174],"methodology":[145,176,199],"is":[146],"validated":[147],"through":[148],"rigorous":[149],"simulations":[150],"at":[151],"process,":[153],"level,":[157],"incorporating":[158],"various":[159],"statistical":[160],"techniques.":[161],"A":[162],"few":[163],"examples":[164],"will":[165,200],"presented":[167],"elaborate":[169],"significance":[171],"its":[178],"utility":[179,192],"Nano":[182],"flow.":[185],"In":[186],"addition":[187],"being":[189],"flow,":[197],"also":[201],"help":[202,224],"foundries":[204],"by":[205],"providing":[206],"visibility":[208],"on":[209,215],"impact":[211],"unit":[213],"processes":[214],"eventual":[217],"characteristics.":[219],"turn":[222],"can":[223],"systematic":[227],"optimized":[229],"monitoring":[231],"foundries.":[234]},"counts_by_year":[],"updated_date":"2026-07-02T09:51:11.867554","created_date":"2025-10-10T00:00:00"}