{"id":"https://openalex.org/W2125154666","doi":"https://doi.org/10.1109/iscas.2009.5118110","title":"Buffer planning for 3D ICs","display_name":"Buffer planning for 3D ICs","publication_year":2009,"publication_date":"2009-05-01","ids":{"openalex":"https://openalex.org/W2125154666","doi":"https://doi.org/10.1109/iscas.2009.5118110","mag":"2125154666"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2009.5118110","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2009.5118110","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5110234701","display_name":"Sheqin Dong","orcid":null},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":true,"raw_author_name":"Sheqin Dong","raw_affiliation_strings":["Department of Compute Science and Technology, Tsinghua University, Beijing, China","Department of Compute Science and Technology, Tsinghua University, Beijing 100084, China"],"affiliations":[{"raw_affiliation_string":"Department of Compute Science and Technology, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089"]},{"raw_affiliation_string":"Department of Compute Science and Technology, Tsinghua University, Beijing 100084, China","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103376597","display_name":"Hongjie Bai","orcid":null},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Hongjie Bai","raw_affiliation_strings":["Department of Compute Science and Technology, Tsinghua University, Beijing, China","Department of Compute Science and Technology, Tsinghua University, Beijing 100084, China"],"affiliations":[{"raw_affiliation_string":"Department of Compute Science and Technology, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089"]},{"raw_affiliation_string":"Department of Compute Science and Technology, Tsinghua University, Beijing 100084, China","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5111914906","display_name":"Xianlong Hong","orcid":null},"institutions":[{"id":"https://openalex.org/I99065089","display_name":"Tsinghua University","ror":"https://ror.org/03cve4549","country_code":"CN","type":"education","lineage":["https://openalex.org/I99065089"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xianlong Hong","raw_affiliation_strings":["Department of Compute Science and Technology, Tsinghua University, Beijing, China","Department of Compute Science and Technology, Tsinghua University, Beijing 100084, China"],"affiliations":[{"raw_affiliation_string":"Department of Compute Science and Technology, Tsinghua University, Beijing, China","institution_ids":["https://openalex.org/I99065089"]},{"raw_affiliation_string":"Department of Compute Science and Technology, Tsinghua University, Beijing 100084, China","institution_ids":["https://openalex.org/I99065089"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101825973","display_name":"Satoshi Goto","orcid":"https://orcid.org/0000-0002-6387-048X"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Satoshi Goto","raw_affiliation_strings":["Graduate School of IPS, Fukuoka, Japan","Graduate School of IPS, Kitakyushu, Fukuoka, Japan"],"affiliations":[{"raw_affiliation_string":"Graduate School of IPS, Fukuoka, Japan","institution_ids":[]},{"raw_affiliation_string":"Graduate School of IPS, Kitakyushu, Fukuoka, Japan","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5110234701"],"corresponding_institution_ids":["https://openalex.org/I99065089"],"apc_list":null,"apc_paid":null,"fwci":0.2991,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.64239399,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1735","last_page":"1738"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/floorplan","display_name":"Floorplan","score":0.9059311151504517},{"id":"https://openalex.org/keywords/buffer","display_name":"Buffer (optical fiber)","score":0.8722149133682251},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.7659375667572021},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.6742302179336548},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6707115173339844},{"id":"https://openalex.org/keywords/integrated-circuit-layout","display_name":"Integrated circuit layout","score":0.5377907752990723},{"id":"https://openalex.org/keywords/path","display_name":"Path (computing)","score":0.4282887578010559},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.42472654581069946},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3964272737503052},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3660650849342346},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.3468923270702362},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.1945735216140747},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1902494728565216},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.09073075652122498},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07999652624130249}],"concepts":[{"id":"https://openalex.org/C130145326","wikidata":"https://www.wikidata.org/wiki/Q1553985","display_name":"Floorplan","level":2,"score":0.9059311151504517},{"id":"https://openalex.org/C145018004","wikidata":"https://www.wikidata.org/wiki/Q4985944","display_name":"Buffer (optical fiber)","level":2,"score":0.8722149133682251},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.7659375667572021},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.6742302179336548},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6707115173339844},{"id":"https://openalex.org/C2765594","wikidata":"https://www.wikidata.org/wiki/Q2624187","display_name":"Integrated circuit layout","level":3,"score":0.5377907752990723},{"id":"https://openalex.org/C2777735758","wikidata":"https://www.wikidata.org/wiki/Q817765","display_name":"Path (computing)","level":2,"score":0.4282887578010559},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.42472654581069946},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3964272737503052},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3660650849342346},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.3468923270702362},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.1945735216140747},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1902494728565216},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.09073075652122498},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07999652624130249}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2009.5118110","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2009.5118110","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/11","score":0.6299999952316284,"display_name":"Sustainable cities and communities"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":28,"referenced_works":["https://openalex.org/W1489808870","https://openalex.org/W1541633348","https://openalex.org/W1850923586","https://openalex.org/W1857834374","https://openalex.org/W2005821086","https://openalex.org/W2064922498","https://openalex.org/W2099932375","https://openalex.org/W2114542420","https://openalex.org/W2123637249","https://openalex.org/W2131979475","https://openalex.org/W2135118255","https://openalex.org/W2140704214","https://openalex.org/W2143199124","https://openalex.org/W2144149750","https://openalex.org/W2153593246","https://openalex.org/W2153770483","https://openalex.org/W2154462472","https://openalex.org/W2160252016","https://openalex.org/W2168506183","https://openalex.org/W2180394037","https://openalex.org/W2183935829","https://openalex.org/W4230562647","https://openalex.org/W6629275814","https://openalex.org/W6638863203","https://openalex.org/W6639047404","https://openalex.org/W6678120071","https://openalex.org/W6682941313","https://openalex.org/W6686439698"],"related_works":["https://openalex.org/W2133901311","https://openalex.org/W2136768364","https://openalex.org/W2087871358","https://openalex.org/W4386643835","https://openalex.org/W2120361800","https://openalex.org/W2182445672","https://openalex.org/W2124495928","https://openalex.org/W2129355781","https://openalex.org/W4363620137","https://openalex.org/W2005457717"],"abstract_inverted_index":{"With":[0],"recent":[1],"advance":[2],"of":[3],"VLSI":[4],"design,":[5],"interconnect":[6,24],"delay":[7],"plays":[8],"dominant":[9],"role":[10],"in":[11],"the":[12,75,81,100],"chip":[13],"performance.":[14],"3D":[15,53,76],"integration,":[16],"which":[17],"stacks":[18],"multiple":[19],"device":[20],"layers,":[21],"greatly":[22],"reduces":[23],"delay.":[25],"Buffer":[26],"insertion,":[27],"as":[28],"another":[29],"approach":[30],"to":[31,38,62,73,98],"reduce":[32,59],"wire":[33,108],"delay,":[34],"is":[35,55,94,116],"still":[36],"necessary":[37],"further":[39],"optimize":[40,99],"interconnects.":[41],"In":[42],"this":[43],"paper,":[44],"a":[45,63,111],"buffer":[46,60,77,92],"planning":[47,93],"algorithm":[48],"at":[49],"floorplanning":[50,97],"stage":[51],"for":[52],"ICs":[54],"proposed.":[56],"Firstly,":[57],"we":[58,69],"insertion":[61,78],"dynamic":[64],"programming":[65],"path":[66],"problem.":[67,79],"Then":[68],"show":[70],"its":[71],"potential":[72],"handle":[74],"At":[80,90],"same":[82],"time,":[83],"vertical":[84],"interlayer":[85],"vias":[86],"are":[87],"also":[88,117],"planned.":[89],"last,":[91],"integrated":[95],"with":[96],"packing":[101],"so":[102],"that":[103],"not":[104],"only":[105],"area":[106],"and":[107],"length":[109],"reach":[110],"satisfying":[112],"value,":[113],"timing":[114],"performance":[115],"optimized.":[118]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}