{"id":"https://openalex.org/W2102695281","doi":"https://doi.org/10.1109/iscas.2009.5117929","title":"A performance comparison on asynchronous matched-delay templates","display_name":"A performance comparison on asynchronous matched-delay templates","publication_year":2009,"publication_date":"2009-05-01","ids":{"openalex":"https://openalex.org/W2102695281","doi":"https://doi.org/10.1109/iscas.2009.5117929","mag":"2102695281"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2009.5117929","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2009.5117929","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5020890655","display_name":"Kok-Leong Chang","orcid":null},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":true,"raw_author_name":"Kok-Leong Chang","raw_affiliation_strings":["Centre of Integrated Circuits and Systems, Nanyang Technological University, Singapore","Centre for Integrated Circuits and Systems, Nanyang Technological University, Singapore"],"affiliations":[{"raw_affiliation_string":"Centre of Integrated Circuits and Systems, Nanyang Technological University, Singapore","institution_ids":["https://openalex.org/I172675005"]},{"raw_affiliation_string":"Centre for Integrated Circuits and Systems, Nanyang Technological University, Singapore","institution_ids":["https://openalex.org/I172675005"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5000314679","display_name":"Bah\u2010Hwee Gwee","orcid":"https://orcid.org/0000-0002-3222-2885"},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Bah-Hwee Gwee","raw_affiliation_strings":["Centre of Integrated Circuits and Systems, Nanyang Technological University, Singapore","Centre for Integrated Circuits and Systems, Nanyang Technological University, Singapore"],"affiliations":[{"raw_affiliation_string":"Centre of Integrated Circuits and Systems, Nanyang Technological University, Singapore","institution_ids":["https://openalex.org/I172675005"]},{"raw_affiliation_string":"Centre for Integrated Circuits and Systems, Nanyang Technological University, Singapore","institution_ids":["https://openalex.org/I172675005"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5016044907","display_name":"Yuanjin Zheng","orcid":"https://orcid.org/0000-0002-5768-367X"},"institutions":[{"id":"https://openalex.org/I4210090209","display_name":"Institute of Microelectronics","ror":"https://ror.org/009rw8n36","country_code":"SG","type":"facility","lineage":["https://openalex.org/I115228651","https://openalex.org/I4210090209","https://openalex.org/I91275662"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Yuanjin Zheng","raw_affiliation_strings":["Institute of Microelectronics, Integrated Circuits and Systems Laboratory, Singapore","Integrated Circuits and Systems Laboratory, Institute of Microelectronics, Singapore"],"affiliations":[{"raw_affiliation_string":"Institute of Microelectronics, Integrated Circuits and Systems Laboratory, Singapore","institution_ids":["https://openalex.org/I4210090209"]},{"raw_affiliation_string":"Integrated Circuits and Systems Laboratory, Institute of Microelectronics, Singapore","institution_ids":["https://openalex.org/I4210090209"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5020890655"],"corresponding_institution_ids":["https://openalex.org/I172675005"],"apc_list":null,"apc_paid":null,"fwci":0.2991,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.63276969,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1008","last_page":"1011"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.9277567863464355},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7288798689842224},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.6701442003250122},{"id":"https://openalex.org/keywords/asynchronous-system","display_name":"Asynchronous system","score":0.5994006395339966},{"id":"https://openalex.org/keywords/template","display_name":"Template","score":0.5878795385360718},{"id":"https://openalex.org/keywords/abstraction","display_name":"Abstraction","score":0.47051137685775757},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.45370855927467346},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4331865608692169},{"id":"https://openalex.org/keywords/limit","display_name":"Limit (mathematics)","score":0.4128771126270294},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.4120132327079773},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3919062912464142},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.36813437938690186},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.14483803510665894},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1420237421989441},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.1406436264514923},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.13685515522956848},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.1297118067741394},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.09217765927314758}],"concepts":[{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.9277567863464355},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7288798689842224},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.6701442003250122},{"id":"https://openalex.org/C7923308","wikidata":"https://www.wikidata.org/wiki/Q4812211","display_name":"Asynchronous system","level":5,"score":0.5994006395339966},{"id":"https://openalex.org/C82714645","wikidata":"https://www.wikidata.org/wiki/Q438331","display_name":"Template","level":2,"score":0.5878795385360718},{"id":"https://openalex.org/C124304363","wikidata":"https://www.wikidata.org/wiki/Q673661","display_name":"Abstraction","level":2,"score":0.47051137685775757},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.45370855927467346},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4331865608692169},{"id":"https://openalex.org/C151201525","wikidata":"https://www.wikidata.org/wiki/Q177239","display_name":"Limit (mathematics)","level":2,"score":0.4128771126270294},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.4120132327079773},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3919062912464142},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.36813437938690186},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.14483803510665894},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1420237421989441},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.1406436264514923},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.13685515522956848},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.1297118067741394},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.09217765927314758},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.0},{"id":"https://openalex.org/C111472728","wikidata":"https://www.wikidata.org/wiki/Q9471","display_name":"Epistemology","level":1,"score":0.0},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2009.5117929","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2009.5117929","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W1583778827","https://openalex.org/W1809169466","https://openalex.org/W1998380797","https://openalex.org/W2025516544","https://openalex.org/W2108964809","https://openalex.org/W2127514448","https://openalex.org/W2132729131","https://openalex.org/W2160160584","https://openalex.org/W2161331676","https://openalex.org/W2168634757","https://openalex.org/W2169222350","https://openalex.org/W2178247634","https://openalex.org/W4231905827","https://openalex.org/W6634853733","https://openalex.org/W6684811046"],"related_works":["https://openalex.org/W4312516786","https://openalex.org/W1502478103","https://openalex.org/W2109350679","https://openalex.org/W1984298705","https://openalex.org/W4247130854","https://openalex.org/W1482079447","https://openalex.org/W2127795343","https://openalex.org/W2119881965","https://openalex.org/W1977181099","https://openalex.org/W1991539879"],"abstract_inverted_index":{"The":[0,142],"motivation":[1],"for":[2],"asynchronous":[3,39,46,91,105],"logic":[4,24],"at":[5,55],"this":[6,99],"juncture":[7],"of":[8,14,29,38,52,59,74,90,120,124,152],"CMOS":[9],"technology":[10],"is":[11,25],"the":[12,34,50,63,72,78,83,87,101],"issues":[13],"power":[15],"density,":[16],"process":[17],"variation":[18],"and":[19,41,43,114,136],"integration":[20],"limit,":[21],"where":[22],"synchronous":[23,67,85],"facing":[26],"a":[27,56,149],"myriad":[28],"problems.":[30],"Asynchronous":[31],"templates":[32],"are":[33],"fundamental":[35],"building":[36],"blocks":[37],"circuits":[40],"systems,":[42],"together":[44],"with":[45],"EDA":[47],"tools":[48],"enable":[49],"design":[51,122],"complex":[53],"systems":[54],"high":[57],"level":[58],"abstraction":[60],"(similar":[61],"to":[62,71,77,109],"RTL-to-GDSII":[64],"flow":[65],"in":[66,82,98],"design).":[68],"However,":[69],"akin":[70],"impact":[73],"library":[75],"cells":[76],"overall":[79],"system":[80],"performance":[81],"conventional":[84],"flow,":[86],"diverse":[88],"availability":[89],"template":[92,106,128,145],"libraries":[93],"requires":[94],"prudent":[95],"contemplation.":[96],"Therefore":[97],"paper,":[100],"most":[102,143],"eminent":[103],"matched-delay":[104],"families":[107],"reported":[108],"date":[110],"will":[111],"be":[112],"presented,":[113],"followed":[115],"by":[116],"an":[117],"in-depth":[118],"comparison":[119],"various":[121],"figure":[123],"merits":[125],"(FOMs)":[126],"-":[127],"area,":[129],"static/dynamic":[130],"capacity,":[131],"cycle":[132],"time,":[133],"latency,":[134],"throughput":[135,151],"Et":[137],"<sup":[138],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[139],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[140],".":[141],"aggressive":[144],"(GasP)":[146],"can":[147],"reach":[148],"maximum":[150],"5":[153],"Giga":[154],"items/s":[155],"on":[156],"0.13":[157],"mum":[158],"@":[159],"1.2":[160],"V.":[161]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}