{"id":"https://openalex.org/W2137530941","doi":"https://doi.org/10.1109/iscas.2009.5117782","title":"Adder circuits with transistors using independently controlled gates","display_name":"Adder circuits with transistors using independently controlled gates","publication_year":2009,"publication_date":"2009-05-01","ids":{"openalex":"https://openalex.org/W2137530941","doi":"https://doi.org/10.1109/iscas.2009.5117782","mag":"2137530941"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2009.5117782","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2009.5117782","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5108536709","display_name":"Marcus Weis","orcid":null},"institutions":[{"id":"https://openalex.org/I62916508","display_name":"Technical University of Munich","ror":"https://ror.org/02kkvpp62","country_code":"DE","type":"education","lineage":["https://openalex.org/I62916508"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Marcus Weis","raw_affiliation_strings":["Technische Universit\u00e4t M\u00fcnchen, Germany","Technische Universitat, Munchen, Germany#TAB#"],"affiliations":[{"raw_affiliation_string":"Technische Universit\u00e4t M\u00fcnchen, Germany","institution_ids":["https://openalex.org/I62916508"]},{"raw_affiliation_string":"Technische Universitat, Munchen, Germany#TAB#","institution_ids":["https://openalex.org/I62916508"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109012607","display_name":"Andrzej Pfitzner","orcid":null},"institutions":[{"id":"https://openalex.org/I108403487","display_name":"Warsaw University of Technology","ror":"https://ror.org/00y0xnp53","country_code":"PL","type":"education","lineage":["https://openalex.org/I108403487"]}],"countries":["PL"],"is_corresponding":false,"raw_author_name":"Andrzej Pfitzner","raw_affiliation_strings":["Warsaw University of Technology, Poland",", , , Warsaw University of Technology, , Poland"],"affiliations":[{"raw_affiliation_string":"Warsaw University of Technology, Poland","institution_ids":["https://openalex.org/I108403487"]},{"raw_affiliation_string":", , , Warsaw University of Technology, , Poland","institution_ids":["https://openalex.org/I108403487"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034089826","display_name":"Dominik Kasprowicz","orcid":"https://orcid.org/0000-0002-3480-6585"},"institutions":[{"id":"https://openalex.org/I108403487","display_name":"Warsaw University of Technology","ror":"https://ror.org/00y0xnp53","country_code":"PL","type":"education","lineage":["https://openalex.org/I108403487"]}],"countries":["PL"],"is_corresponding":false,"raw_author_name":"Dominik Kasprowicz","raw_affiliation_strings":["Warsaw University of Technology, Poland",", , , Warsaw University of Technology, , Poland"],"affiliations":[{"raw_affiliation_string":"Warsaw University of Technology, Poland","institution_ids":["https://openalex.org/I108403487"]},{"raw_affiliation_string":", , , Warsaw University of Technology, , Poland","institution_ids":["https://openalex.org/I108403487"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5068965796","display_name":"R. Emling","orcid":null},"institutions":[{"id":"https://openalex.org/I62916508","display_name":"Technical University of Munich","ror":"https://ror.org/02kkvpp62","country_code":"DE","type":"education","lineage":["https://openalex.org/I62916508"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Rainer Emling","raw_affiliation_strings":["Technische Universit\u00e4t M\u00fcnchen, Germany","Technische Universitat, Munchen, Germany#TAB#"],"affiliations":[{"raw_affiliation_string":"Technische Universit\u00e4t M\u00fcnchen, Germany","institution_ids":["https://openalex.org/I62916508"]},{"raw_affiliation_string":"Technische Universitat, Munchen, Germany#TAB#","institution_ids":["https://openalex.org/I62916508"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5013238154","display_name":"W. Maly","orcid":null},"institutions":[{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Wojciech Maly","raw_affiliation_strings":["Carnegie Mellon University, Pittsburgh, USA"],"affiliations":[{"raw_affiliation_string":"Carnegie Mellon University, Pittsburgh, USA","institution_ids":["https://openalex.org/I74973139"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5034576088","display_name":"D. Schmitt\u2010Landsiedel","orcid":"https://orcid.org/0000-0002-4817-5139"},"institutions":[{"id":"https://openalex.org/I62916508","display_name":"Technical University of Munich","ror":"https://ror.org/02kkvpp62","country_code":"DE","type":"education","lineage":["https://openalex.org/I62916508"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Doris Schmitt-Landsiedel","raw_affiliation_strings":["Technische Universit\u00e4t M\u00fcnchen, Germany","Technische Universitat, Munchen, Germany#TAB#"],"affiliations":[{"raw_affiliation_string":"Technische Universit\u00e4t M\u00fcnchen, Germany","institution_ids":["https://openalex.org/I62916508"]},{"raw_affiliation_string":"Technische Universitat, Munchen, Germany#TAB#","institution_ids":["https://openalex.org/I62916508"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5108536709"],"corresponding_institution_ids":["https://openalex.org/I62916508"],"apc_list":null,"apc_paid":null,"fwci":2.3926,"has_fulltext":false,"cited_by_count":15,"citation_normalized_percentile":{"value":0.89316402,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"449","last_page":"452"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.8613176345825195},{"id":"https://openalex.org/keywords/transistor-count","display_name":"Transistor count","score":0.7709205150604248},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.7059133052825928},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.6169333457946777},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.6058846712112427},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5978571176528931},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5731579661369324},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5243663787841797},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.4239605665206909},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.4160362482070923},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.27274125814437866},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.25919079780578613},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.24236655235290527},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1687425673007965}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.8613176345825195},{"id":"https://openalex.org/C196320899","wikidata":"https://www.wikidata.org/wiki/Q2623746","display_name":"Transistor count","level":4,"score":0.7709205150604248},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.7059133052825928},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.6169333457946777},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.6058846712112427},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5978571176528931},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5731579661369324},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5243663787841797},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.4239605665206909},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.4160362482070923},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.27274125814437866},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.25919079780578613},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.24236655235290527},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1687425673007965},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2009.5117782","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2009.5117782","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8899999856948853}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1518236483","https://openalex.org/W1594700695","https://openalex.org/W2127587406","https://openalex.org/W2141803235","https://openalex.org/W2147847555","https://openalex.org/W2898386585","https://openalex.org/W6756448661"],"related_works":["https://openalex.org/W3166220017","https://openalex.org/W2119296295","https://openalex.org/W2622611104","https://openalex.org/W2595074880","https://openalex.org/W2394021504","https://openalex.org/W2163456301","https://openalex.org/W4206995395","https://openalex.org/W2897293593","https://openalex.org/W2140092109","https://openalex.org/W2526565644"],"abstract_inverted_index":{"Circuits":[0],"with":[1],"transistors":[2,15,46],"using":[3],"independently":[4],"controlled":[5],"gates":[6],"have":[7,30],"been":[8,31],"proposed":[9],"to":[10,17],"reduce":[11],"the":[12,19,37,40,60],"number":[13],"of":[14,42],"and":[16,52,59,66,72],"increase":[18],"logic":[20],"density":[21],"per":[22],"area.":[23],"So":[24],"far":[25],"only":[26],"small":[27],"building":[28],"blocks":[29],"presented.":[32,70],"This":[33],"paper":[34],"investigates":[35],"for":[36],"first":[38],"time":[39],"use":[41],"independent":[43],"double":[44],"gate":[45],"in":[47],"16":[48],"bit":[49],"ripple":[50],"carry":[51],"parallel":[53],"prefix":[54],"adders.":[55],"New":[56],"adder":[57],"circuits":[58],"trade-off":[61],"between":[62],"area":[63],"reduction,":[64],"delay":[65],"power":[67],"consumption":[68],"are":[69],"Area":[71],"transistor":[73],"count":[74],"reduction":[75],"by":[76],"one":[77],"third":[78],"can":[79],"be":[80],"achieved.":[81]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}