{"id":"https://openalex.org/W2167870772","doi":"https://doi.org/10.1109/iscas.2009.5117752","title":"High-frequency systolic broadband beamforming using polyphase 3D IIR frequency-planar digital filters with interleaved A/D sampling","display_name":"High-frequency systolic broadband beamforming using polyphase 3D IIR frequency-planar digital filters with interleaved A/D sampling","publication_year":2009,"publication_date":"2009-05-01","ids":{"openalex":"https://openalex.org/W2167870772","doi":"https://doi.org/10.1109/iscas.2009.5117752","mag":"2167870772"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2009.5117752","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2009.5117752","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5064035420","display_name":"Arjuna Madanayake","orcid":"https://orcid.org/0000-0003-3478-6702"},"institutions":[{"id":"https://openalex.org/I168635309","display_name":"University of Calgary","ror":"https://ror.org/03yjb2x39","country_code":"CA","type":"education","lineage":["https://openalex.org/I168635309"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"H.L.P. Arjuna Madanayake","raw_affiliation_strings":["Electrical and Computer Engineering, University of Calgary, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering, University of Calgary, Canada","institution_ids":["https://openalex.org/I168635309"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063673747","display_name":"Thushara Gunaratne","orcid":"https://orcid.org/0000-0001-6636-1296"},"institutions":[{"id":"https://openalex.org/I168635309","display_name":"University of Calgary","ror":"https://ror.org/03yjb2x39","country_code":"CA","type":"education","lineage":["https://openalex.org/I168635309"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Thushara K. Gunaratne","raw_affiliation_strings":["Electrical and Computer Engineering, University of Calgary, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering, University of Calgary, Canada","institution_ids":["https://openalex.org/I168635309"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111429082","display_name":"L.T. Bruton","orcid":null},"institutions":[{"id":"https://openalex.org/I168635309","display_name":"University of Calgary","ror":"https://ror.org/03yjb2x39","country_code":"CA","type":"education","lineage":["https://openalex.org/I168635309"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Len T. Bruton","raw_affiliation_strings":["Electrical and Computer Engineering, University of Calgary, Canada"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical and Computer Engineering, University of Calgary, Canada","institution_ids":["https://openalex.org/I168635309"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.21474465,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"130","issue":null,"first_page":"329","last_page":"332"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11383","display_name":"Advanced Antenna and Metasurface Technologies","score":0.9948999881744385,"subfield":{"id":"https://openalex.org/subfields/2202","display_name":"Aerospace Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11946","display_name":"Antenna Design and Optimization","score":0.9944999814033508,"subfield":{"id":"https://openalex.org/subfields/2202","display_name":"Aerospace Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/polyphase-system","display_name":"Polyphase system","score":0.7998223304748535},{"id":"https://openalex.org/keywords/beamforming","display_name":"Beamforming","score":0.684745728969574},{"id":"https://openalex.org/keywords/infinite-impulse-response","display_name":"Infinite impulse response","score":0.6259037852287292},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5689327716827393},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.5052722096443176},{"id":"https://openalex.org/keywords/frame-rate","display_name":"Frame rate","score":0.48365840315818787},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.4679773151874542},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.46141064167022705},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.41445720195770264},{"id":"https://openalex.org/keywords/digital-filter","display_name":"Digital filter","score":0.3756595253944397},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3345310688018799},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.2045055329799652},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.20170867443084717},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.16484194993972778},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.155294269323349},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.09084555506706238}],"concepts":[{"id":"https://openalex.org/C96157337","wikidata":"https://www.wikidata.org/wiki/Q391639","display_name":"Polyphase system","level":2,"score":0.7998223304748535},{"id":"https://openalex.org/C54197355","wikidata":"https://www.wikidata.org/wiki/Q5782992","display_name":"Beamforming","level":2,"score":0.684745728969574},{"id":"https://openalex.org/C183816354","wikidata":"https://www.wikidata.org/wiki/Q665617","display_name":"Infinite impulse response","level":4,"score":0.6259037852287292},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5689327716827393},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.5052722096443176},{"id":"https://openalex.org/C3261483","wikidata":"https://www.wikidata.org/wiki/Q119565","display_name":"Frame rate","level":2,"score":0.48365840315818787},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.4679773151874542},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.46141064167022705},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.41445720195770264},{"id":"https://openalex.org/C36390408","wikidata":"https://www.wikidata.org/wiki/Q1163067","display_name":"Digital filter","level":3,"score":0.3756595253944397},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3345310688018799},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.2045055329799652},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.20170867443084717},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16484194993972778},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.155294269323349},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.09084555506706238},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2009.5117752","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2009.5117752","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.550000011920929,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1481646516","https://openalex.org/W1501488688","https://openalex.org/W1821096973","https://openalex.org/W1898662204","https://openalex.org/W1965593120","https://openalex.org/W1988829363","https://openalex.org/W2043299190","https://openalex.org/W2099652181","https://openalex.org/W2108051085","https://openalex.org/W2109675279","https://openalex.org/W2138879089","https://openalex.org/W4246482746","https://openalex.org/W6680589242"],"related_works":["https://openalex.org/W1570168341","https://openalex.org/W2067519269","https://openalex.org/W1511779429","https://openalex.org/W2810377961","https://openalex.org/W1527963436","https://openalex.org/W762710671","https://openalex.org/W2154498341","https://openalex.org/W2912776486","https://openalex.org/W2487154765","https://openalex.org/W4255185097"],"abstract_inverted_index":{"A":[0],"massively-parallel":[1],"polyphase":[2],"systolic":[3,98,106],"array":[4,99],"processor":[5,89],"is":[6,20,37,90,101],"proposed":[7],"for":[8],"broadband":[9,62],"beamforming":[10,66],"using":[11,92],"a":[12,25,93,97,104,122,136,142],"3D":[13],"IIR":[14],"space-time":[15],"digital":[16,65],"frequency-planar":[17],"filter":[18],"that":[19,70],"capable":[21],"of":[22,27,40,79,87,96,103,121,125,147],"operating":[23],"at":[24,67,153],"throughput":[26,49],"M":[28,36],"2D":[29],"spatial":[30,145],"frames":[31],"every":[32],"clock":[33,77],"cycle,":[34],"where":[35],"the":[38,57,76,80,88],"number":[39],"(poly)phases.":[41],"The":[42,83],"method":[43],"achieves":[44],"an":[45],"M-fold":[46],"increase":[47],"in":[48],"relative":[50],"to":[51,59],"previously":[52],"known":[53],"architectures,":[54],"and":[55],"has":[56],"potential":[58],"achieve":[60],"highly-selective":[61],"radio-frequency":[63],"(RF)":[64],"frame":[68],"rates":[69],"are":[71],"several":[72],"times":[73],"greater":[74],"than":[75],"rate":[78],"VLSI":[81],"system.":[82],"practical":[84],"real-time":[85],"performance":[86],"demonstrated":[91],"3\u00d73":[94],"section":[95],"(that":[100],"part":[102],"larger":[105],"N":[107,112],"<inf":[108,113],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[109,114],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">1</inf>":[110],"\u00d7":[111,117],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</inf>":[115],"\u2248100":[116],"100":[118,148],"system),":[119],"consisting":[120],"locally-interconnected":[123],"matrix":[124],"9":[126],"identical":[127],"fully-pipelined":[128],"speed-optimized":[129],"two":[130],"phase":[131],"(M=2)":[132],"parallel":[133],"processors":[134],"on":[135],"Xilinx":[137],"Sx35":[138],"FPGA":[139],"device,":[140],"having":[141],"corresponding":[143],"measured":[144],"frame-rate":[146],"million":[149],"frames/second,":[150],"when":[151],"clocked":[152],"50":[154],"MHz.":[155]},"counts_by_year":[],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}