{"id":"https://openalex.org/W2137913796","doi":"https://doi.org/10.1109/iscas.2009.5117714","title":"Design and optimization of a 71 Gb/s injection-locked CDR","display_name":"Design and optimization of a 71 Gb/s injection-locked CDR","publication_year":2009,"publication_date":"2009-05-01","ids":{"openalex":"https://openalex.org/W2137913796","doi":"https://doi.org/10.1109/iscas.2009.5117714","mag":"2137913796"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2009.5117714","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2009.5117714","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5087319221","display_name":"Tonmoy S. Mukherjee","orcid":null},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Tonmoy S. Mukherjee","raw_affiliation_strings":["School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA","School of Electrical and Computer Engineering Georgia Institute of Technology, Atlanta, 30332-0250, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA","institution_ids":["https://openalex.org/I130701444"]},{"raw_affiliation_string":"School of Electrical and Computer Engineering Georgia Institute of Technology, Atlanta, 30332-0250, USA","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5062985403","display_name":"M. Omer","orcid":null},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mohammad Omer","raw_affiliation_strings":["School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA","School of Electrical and Computer Engineering Georgia Institute of Technology, Atlanta, 30332-0250, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA","institution_ids":["https://openalex.org/I130701444"]},{"raw_affiliation_string":"School of Electrical and Computer Engineering Georgia Institute of Technology, Atlanta, 30332-0250, USA","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100451545","display_name":"Jihwan Kim","orcid":"https://orcid.org/0000-0002-5599-2997"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jihwan Kim","raw_affiliation_strings":["School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA","School of Electrical and Computer Engineering Georgia Institute of Technology, Atlanta, 30332-0250, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA","institution_ids":["https://openalex.org/I130701444"]},{"raw_affiliation_string":"School of Electrical and Computer Engineering Georgia Institute of Technology, Atlanta, 30332-0250, USA","institution_ids":["https://openalex.org/I130701444"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5063608429","display_name":"Kevin Kornegay","orcid":"https://orcid.org/0000-0002-5233-0154"},"institutions":[{"id":"https://openalex.org/I130701444","display_name":"Georgia Institute of Technology","ror":"https://ror.org/01zkghx44","country_code":"US","type":"education","lineage":["https://openalex.org/I130701444"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kevin T. Kornegay","raw_affiliation_strings":["School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA","School of Electrical and Computer Engineering Georgia Institute of Technology, Atlanta, 30332-0250, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA","institution_ids":["https://openalex.org/I130701444"]},{"raw_affiliation_string":"School of Electrical and Computer Engineering Georgia Institute of Technology, Atlanta, 30332-0250, USA","institution_ids":["https://openalex.org/I130701444"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.3052,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.65504808,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":"15","issue":null,"first_page":"177","last_page":"180"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6294369697570801},{"id":"https://openalex.org/keywords/circuit-design","display_name":"Circuit design","score":0.5895289778709412},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5395580530166626},{"id":"https://openalex.org/keywords/wireline","display_name":"Wireline","score":0.5315707921981812},{"id":"https://openalex.org/keywords/circuit-complexity","display_name":"Circuit complexity","score":0.5226759314537048},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.4906264841556549},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.473396897315979},{"id":"https://openalex.org/keywords/asynchronous-circuit","display_name":"Asynchronous circuit","score":0.4426955580711365},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.4367360472679138},{"id":"https://openalex.org/keywords/circuit-extraction","display_name":"Circuit extraction","score":0.4347511827945709},{"id":"https://openalex.org/keywords/physical-design","display_name":"Physical design","score":0.42840200662612915},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.41085392236709595},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.3080597221851349},{"id":"https://openalex.org/keywords/equivalent-circuit","display_name":"Equivalent circuit","score":0.2838021516799927},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2714548110961914},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.24827763438224792},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.24289336800575256},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.200813889503479},{"id":"https://openalex.org/keywords/wireless","display_name":"Wireless","score":0.1207025945186615},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.11467626690864563}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6294369697570801},{"id":"https://openalex.org/C190560348","wikidata":"https://www.wikidata.org/wiki/Q3245116","display_name":"Circuit design","level":2,"score":0.5895289778709412},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5395580530166626},{"id":"https://openalex.org/C2776951270","wikidata":"https://www.wikidata.org/wiki/Q8026910","display_name":"Wireline","level":3,"score":0.5315707921981812},{"id":"https://openalex.org/C90702460","wikidata":"https://www.wikidata.org/wiki/Q1055112","display_name":"Circuit complexity","level":3,"score":0.5226759314537048},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.4906264841556549},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.473396897315979},{"id":"https://openalex.org/C87695204","wikidata":"https://www.wikidata.org/wiki/Q629971","display_name":"Asynchronous circuit","level":5,"score":0.4426955580711365},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.4367360472679138},{"id":"https://openalex.org/C26490066","wikidata":"https://www.wikidata.org/wiki/Q17006835","display_name":"Circuit extraction","level":4,"score":0.4347511827945709},{"id":"https://openalex.org/C188817802","wikidata":"https://www.wikidata.org/wiki/Q13426855","display_name":"Physical design","level":3,"score":0.42840200662612915},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.41085392236709595},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.3080597221851349},{"id":"https://openalex.org/C23572009","wikidata":"https://www.wikidata.org/wiki/Q964981","display_name":"Equivalent circuit","level":3,"score":0.2838021516799927},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2714548110961914},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.24827763438224792},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.24289336800575256},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.200813889503479},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.1207025945186615},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.11467626690864563}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2009.5117714","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2009.5117714","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8899999856948853,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1967266690","https://openalex.org/W2074088907","https://openalex.org/W2116099132","https://openalex.org/W2118946652","https://openalex.org/W2129102896","https://openalex.org/W2156148457","https://openalex.org/W2170165409","https://openalex.org/W6679203573"],"related_works":["https://openalex.org/W2384756109","https://openalex.org/W364924225","https://openalex.org/W4386292891","https://openalex.org/W2237508561","https://openalex.org/W2590986178","https://openalex.org/W1993985975","https://openalex.org/W4312516786","https://openalex.org/W2373248727","https://openalex.org/W142020038","https://openalex.org/W2377749234"],"abstract_inverted_index":{"High":[0],"data":[1],"rate":[2],"wireline":[3],"systems":[4],"suffer":[5],"from":[6,138],"increasing":[7],"complexity":[8],"and":[9,17,19,30,62,70,84,108,126],"design":[10,64,115,129],"difficulty":[11],"due":[12],"to":[13,33,44,102],"stringent":[14],"system":[15,31,61,127],"specifications":[16],"circuit":[18,29,63,73,106,125,135,143],"technology":[20],"challenges.":[21],"A":[22],"methodology":[23,116],"therefore":[24],"must":[25],"exist":[26],"which":[27],"allows":[28],"challenges":[32],"be":[34],"dealt":[35],"in":[36,75,105],"an":[37,93,120],"effective":[38],"manner":[39],"while":[40],"paying":[41],"close":[42],"attention":[43],"the":[45,58,134,149],"extensive":[46],"coupling":[47],"between":[48,124],"these":[49],"two":[50],"domain.":[51],"In":[52],"this":[53,91],"work":[54],"we":[55],"look":[56],"at":[57],"problem":[59],"of":[60,65,133],"a":[66,76,103],"71":[67],"Gb/s":[68],"Clock":[69],"Data":[71],"Recovery":[72],"(CDR)":[74],"180nm":[77],"SiGe":[78],"process.":[79],"To":[80],"provide":[81],"power":[82,109],"efficient":[83],"robust":[85],"clock":[86],"recovery":[87],"(CR)":[88],"circuits":[89],"for":[90,148],"system,":[92],"injection":[94],"locked":[95],"CR":[96],"block":[97],"has":[98],"been":[99],"implemented,":[100],"leading":[101],"reduction":[104],"components":[107],"consumption":[110],"over":[111],"conventional":[112],"CDRs.":[113],"The":[114,131,141],"is":[117],"based":[118],"on":[119],"iterative":[121],"approach":[122],"alternating":[123],"level":[128],"optimization.":[130],"core":[132],"consumes":[136,144],"136mW":[137],"3.3V":[139],"supply.":[140],"total":[142],"514mW,":[145],"including":[146],"60mW":[147],"limiting":[150],"amplifiers.":[151]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}