{"id":"https://openalex.org/W2159126185","doi":"https://doi.org/10.1109/iscas.2008.4542197","title":"ADAPTO: full-adder based reconfigurable architecture for bit level operations","display_name":"ADAPTO: full-adder based reconfigurable architecture for bit level operations","publication_year":2008,"publication_date":"2008-05-01","ids":{"openalex":"https://openalex.org/W2159126185","doi":"https://doi.org/10.1109/iscas.2008.4542197","mag":"2159126185"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2008.4542197","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2008.4542197","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5028297120","display_name":"G.C. Cardarilli","orcid":"https://orcid.org/0000-0002-7444-876X"},"institutions":[{"id":"https://openalex.org/I116067653","display_name":"University of Rome Tor Vergata","ror":"https://ror.org/02p77k626","country_code":"IT","type":"education","lineage":["https://openalex.org/I116067653"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"G.C. Cardarilli","raw_affiliation_strings":["Department of Electronic Eng., University of Rome Tor Vergata, Via del Politecnico1, 00133, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronic Eng., University of Rome Tor Vergata, Via del Politecnico1, 00133, Italy","institution_ids":["https://openalex.org/I116067653"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063300969","display_name":"Luca Di Nunzio","orcid":"https://orcid.org/0000-0002-4312-7939"},"institutions":[{"id":"https://openalex.org/I116067653","display_name":"University of Rome Tor Vergata","ror":"https://ror.org/02p77k626","country_code":"IT","type":"education","lineage":["https://openalex.org/I116067653"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"L. Di Nunzio","raw_affiliation_strings":["Department of Electronic Eng., University of Rome Tor Vergata, Via del Politecnico1, 00133, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronic Eng., University of Rome Tor Vergata, Via del Politecnico1, 00133, Italy","institution_ids":["https://openalex.org/I116067653"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5000963583","display_name":"M. Re","orcid":"https://orcid.org/0000-0001-9046-1318"},"institutions":[{"id":"https://openalex.org/I116067653","display_name":"University of Rome Tor Vergata","ror":"https://ror.org/02p77k626","country_code":"IT","type":"education","lineage":["https://openalex.org/I116067653"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"M. Re","raw_affiliation_strings":["Department of Electronic Eng., University of Rome Tor Vergata, Via del Politecnico1, 00133, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electronic Eng., University of Rome Tor Vergata, Via del Politecnico1, 00133, Italy","institution_ids":["https://openalex.org/I116067653"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5022318517","display_name":"Alberto Nannarelli","orcid":"https://orcid.org/0000-0002-8303-6329"},"institutions":[{"id":"https://openalex.org/I96673099","display_name":"Technical University of Denmark","ror":"https://ror.org/04qtj9h94","country_code":"DK","type":"education","lineage":["https://openalex.org/I96673099"]}],"countries":["DK"],"is_corresponding":false,"raw_author_name":"Alberto Nannarelli","raw_affiliation_strings":["Department of Informatics & Math Modelling, Technical University of Denmark, Kongens Lyngby, Denmark"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Informatics & Math Modelling, Technical University of Denmark, Kongens Lyngby, Denmark","institution_ids":["https://openalex.org/I96673099"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.9394,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.74252199,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"3434","last_page":"3437"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8029879927635193},{"id":"https://openalex.org/keywords/control-reconfiguration","display_name":"Control reconfiguration","score":0.7153235673904419},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.6735143065452576},{"id":"https://openalex.org/keywords/coprocessor","display_name":"Coprocessor","score":0.6477596759796143},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6381165385246277},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5447787046432495},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.5250874757766724},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.47410279512405396},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4048493206501007},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3561546802520752},{"id":"https://openalex.org/keywords/latency","display_name":"Latency (audio)","score":0.19604220986366272}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8029879927635193},{"id":"https://openalex.org/C119701452","wikidata":"https://www.wikidata.org/wiki/Q5165881","display_name":"Control reconfiguration","level":2,"score":0.7153235673904419},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.6735143065452576},{"id":"https://openalex.org/C86111242","wikidata":"https://www.wikidata.org/wiki/Q859595","display_name":"Coprocessor","level":2,"score":0.6477596759796143},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6381165385246277},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5447787046432495},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.5250874757766724},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.47410279512405396},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4048493206501007},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3561546802520752},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.19604220986366272},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iscas.2008.4542197","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2008.4542197","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},{"id":"pmh:oai:art.torvergata.it:2108/292976","is_oa":false,"landing_page_url":"http://hdl.handle.net/2108/292976","pdf_url":null,"source":{"id":"https://openalex.org/S4306400993","display_name":"Cineca Institutional Research Information System (Tor Vergata University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I116067653","host_organization_name":"University of Rome Tor Vergata","host_organization_lineage":["https://openalex.org/I116067653"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320322454","display_name":"Otto M\u00f8nsteds Fond","ror":"https://ror.org/02dt42634"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1747765598","https://openalex.org/W1882870471","https://openalex.org/W1891709150","https://openalex.org/W2097145429","https://openalex.org/W2098129944","https://openalex.org/W2148911285","https://openalex.org/W2164939754","https://openalex.org/W4252466729","https://openalex.org/W6674764217"],"related_works":["https://openalex.org/W2808484818","https://openalex.org/W2810427553","https://openalex.org/W2135053878","https://openalex.org/W2941434274","https://openalex.org/W2340647897","https://openalex.org/W4249632163","https://openalex.org/W1760305469","https://openalex.org/W2797161794","https://openalex.org/W2073075351","https://openalex.org/W2096938998"],"abstract_inverted_index":{"Low":[0],"cost":[1,134],"microprocessors":[2,131],"and":[3,11,85,109,162,179,205],"DSPs":[4,135],"are":[5,34,79],"optimized":[6],"to":[7,42,77,93,103,136,157,168],"perform":[8],"general":[9],"arithmetic":[10],"logic":[12],"operations":[13],"on":[14,51,200],"native":[15],"wordlength.":[16],"On":[17],"the":[18,21,48,70,94,138,141,159,163,183,207],"other":[19],"hand,":[20],"efficiency":[22],"decreases":[23],"when":[24],"they":[25],"process":[26],"shorter":[27],"data":[28],"(more":[29],"clock":[30,186],"cycles":[31],"per":[32],"operation":[33],"required).":[35],"Recently":[36],"different":[37],"solutions":[38],"have":[39],"been":[40,191],"proposed":[41],"overcome":[43],"this":[44,90],"problem.":[45],"Among":[46],"those,":[47],"one":[49],"based":[50,171,199],"a":[52,56,106,121,195],"main":[53],"processor":[54,185],"with":[55,166],"Reconfigurable":[57,172],"Unit":[58],"(RU)":[59],"used":[60],"as":[61],"coprocessor":[62],"(to":[63],"speed":[64],"up":[65],"fine":[66],"grained":[67],"operations)":[68],"is":[69,101,156],"most":[71],"common.":[72],"Typically":[73],"those":[74],"coprocessors,":[75],"similar":[76],"FPGA,":[78],"composed":[80],"by":[81,193],"Look-Up":[82],"Tables":[83],"(LUTs)":[84],"pass":[86],"transistors":[87],"interconnects.":[88],"In":[89],"way,":[91],"due":[92],"great":[95],"number":[96],"of":[97,140,147],"reconfiguration":[98,108,164,178],"bits,":[99],"it":[100],"impossible":[102],"obtain":[104],"together":[105],"run-time":[107],"an":[110],"efficient":[111],"implementation,":[112],"avoiding":[113],"idle":[114],"hardware":[115,160,177],"resources":[116],".":[117],"This":[118,188],"paper":[119],"proposes":[120],"new":[122,196],"dynamic":[123],"reconfigurable":[124,197],"architecture":[125],"that":[126],"can":[127],"be":[128],"embedded":[129],"in":[130,182],"or":[132],"low":[133],"accelerate":[137],"execution":[139,181],"above":[142],"mentioned":[143],"operations.":[144],"The":[145],"goal":[146,189],"ADAPTO":[148,174],"(Adder-based":[149],"Dynamic":[150],"Architecture":[151],"for":[152],"Processing":[153],"Tailored":[154],"Operators)":[155],"reduce":[158],"complexity":[161],"time,":[165],"respect":[167],"typical":[169],"LUT":[170],"array.":[173],"supports":[175],"both":[176],"instruction":[180],"same":[184],"cycle.":[187],"has":[190],"obtained":[192],"using":[194],"unit":[198],"full":[201],"adders,":[202],"instead":[203],"LUTs,":[204],"simplifying":[206],"network":[208],"interconnect.":[209]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
