{"id":"https://openalex.org/W2138771272","doi":"https://doi.org/10.1109/iscas.2008.4542188","title":"A semi-custom memory design for an asynchronous 8051 microcontroller","display_name":"A semi-custom memory design for an asynchronous 8051 microcontroller","publication_year":2008,"publication_date":"2008-05-01","ids":{"openalex":"https://openalex.org/W2138771272","doi":"https://doi.org/10.1109/iscas.2008.4542188","mag":"2138771272"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2008.4542188","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2008.4542188","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5020890655","display_name":"Kok-Leong Chang","orcid":null},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":true,"raw_author_name":"Kok-Leong Chang","raw_affiliation_strings":["Centre for Integrated Circuits and Systems, Nanyang Technological University, Singapore"],"affiliations":[{"raw_affiliation_string":"Centre for Integrated Circuits and Systems, Nanyang Technological University, Singapore","institution_ids":["https://openalex.org/I172675005"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5000314679","display_name":"Bah\u2010Hwee Gwee","orcid":"https://orcid.org/0000-0002-3222-2885"},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Bah-Hwee Gwee","raw_affiliation_strings":["Centre for Integrated Circuits and Systems, Nanyang Technological University, Singapore"],"affiliations":[{"raw_affiliation_string":"Centre for Integrated Circuits and Systems, Nanyang Technological University, Singapore","institution_ids":["https://openalex.org/I172675005"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5016044907","display_name":"Yuanjin Zheng","orcid":"https://orcid.org/0000-0002-5768-367X"},"institutions":[{"id":"https://openalex.org/I4210090209","display_name":"Institute of Microelectronics","ror":"https://ror.org/009rw8n36","country_code":"SG","type":"facility","lineage":["https://openalex.org/I115228651","https://openalex.org/I4210090209","https://openalex.org/I91275662"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Yuanjin Zheng","raw_affiliation_strings":["Integrated Circuits and Systems Laboratory, Institute of Microelectronics, Singapore"],"affiliations":[{"raw_affiliation_string":"Integrated Circuits and Systems Laboratory, Institute of Microelectronics, Singapore","institution_ids":["https://openalex.org/I4210090209"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5020890655"],"corresponding_institution_ids":["https://openalex.org/I172675005"],"apc_list":null,"apc_paid":null,"fwci":0.9988,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.78904489,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"3398","last_page":"3401"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7637473344802856},{"id":"https://openalex.org/keywords/microcontroller","display_name":"Microcontroller","score":0.6036416292190552},{"id":"https://openalex.org/keywords/memory-refresh","display_name":"Memory refresh","score":0.5846468210220337},{"id":"https://openalex.org/keywords/asynchronous-communication","display_name":"Asynchronous communication","score":0.5622828006744385},{"id":"https://openalex.org/keywords/sense-amplifier","display_name":"Sense amplifier","score":0.5178106427192688},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.5160174369812012},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4903128445148468},{"id":"https://openalex.org/keywords/interfacing","display_name":"Interfacing","score":0.48238101601600647},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4532400965690613},{"id":"https://openalex.org/keywords/computer-memory","display_name":"Computer memory","score":0.3343338668346405}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7637473344802856},{"id":"https://openalex.org/C173018170","wikidata":"https://www.wikidata.org/wiki/Q165678","display_name":"Microcontroller","level":2,"score":0.6036416292190552},{"id":"https://openalex.org/C87907426","wikidata":"https://www.wikidata.org/wiki/Q6815755","display_name":"Memory refresh","level":4,"score":0.5846468210220337},{"id":"https://openalex.org/C151319957","wikidata":"https://www.wikidata.org/wiki/Q752739","display_name":"Asynchronous communication","level":2,"score":0.5622828006744385},{"id":"https://openalex.org/C32666082","wikidata":"https://www.wikidata.org/wiki/Q7450979","display_name":"Sense amplifier","level":3,"score":0.5178106427192688},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.5160174369812012},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4903128445148468},{"id":"https://openalex.org/C2776303644","wikidata":"https://www.wikidata.org/wiki/Q1020499","display_name":"Interfacing","level":2,"score":0.48238101601600647},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4532400965690613},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.3343338668346405},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2008.4542188","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2008.4542188","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8100000023841858,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320309398","display_name":"California Institute of Technology","ror":"https://ror.org/05dxps055"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1567324233","https://openalex.org/W1809169466","https://openalex.org/W2002840706","https://openalex.org/W2049928989","https://openalex.org/W2086743684","https://openalex.org/W2103842380","https://openalex.org/W2104105510","https://openalex.org/W2108454771","https://openalex.org/W2126590585","https://openalex.org/W2153566178","https://openalex.org/W2157881844","https://openalex.org/W6682936363"],"related_works":["https://openalex.org/W4232117715","https://openalex.org/W4242495027","https://openalex.org/W2100773763","https://openalex.org/W2898989424","https://openalex.org/W2181798140","https://openalex.org/W4285257158","https://openalex.org/W4238754064","https://openalex.org/W1999970010","https://openalex.org/W4318328868","https://openalex.org/W4239620147"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"we":[3],"propose":[4],"a":[5],"methodology":[6],"for":[7,49],"interfacing":[8],"synchronous":[9,90],"IP":[10,46,70],"memory":[11,14,18,30,47,71,93],"blocks":[12,31,48],"(read-only":[13],"(ROM)":[15],"and":[16,33,84,87,96,106,132],"random-access":[17],"(RAM))":[19],"with":[20,44,102,142],"asynchronous-logic":[21],"digital":[22],"systems":[23],"based":[24],"on":[25],"dual-rail,":[26],"4-phase":[27,80],"signaling.":[28],"The":[29,100],"(ROM":[32],"RAM)":[34],"of":[35,60,116],"an":[36],"instruction-set":[37],"compatible":[38],"8051":[39],"microcontroller":[40],"(A8051)":[41],"is":[42],"implemented":[43],"Artisan":[45],"the":[50,58,64,69,103,140],"IBM":[51],"0.13\u03bcm":[52],"CMOS":[53],"technology.":[54],"Interface":[55],"circuits":[56],"play":[57],"role":[59],"(1)":[61],"synchronizing":[62],"all":[63],"asynchronous":[65,98],"input":[66],"channels":[67],"driving":[68,97],"blocks,":[72],"(2)":[73],"single":[74],"rail":[75],"signaling":[76,81],"logic":[77,82],"to":[78,139],"dual-rail":[79],"conversion":[83],"vice":[85],"versa,":[86],"(3)":[88],"capturing":[89],"signals":[91],"in":[92],"read":[94],"cycles":[95],"channels.":[99],"A8051":[101,141],"proposed":[104],"ROM":[105],"RAM":[107],"design":[108],"operates":[109],"at":[110],"28%":[111],"higher":[112],"MIPS":[113],"rate":[114],"(millions":[115],"instructions":[117],"per":[118,124],"second),":[119],"dissipates":[120],"20%":[121],"lower":[122,127],"energy":[123],"instruction,":[125],"\u223c50%":[126],"Et":[128],"<sup":[129],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[130],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[131],"occupies":[133],"19%":[134],"lesser":[135],"area,":[136],"as":[137],"compared":[138],"register-based":[143],"memory.":[144]},"counts_by_year":[{"year":2019,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}