{"id":"https://openalex.org/W2167232675","doi":"https://doi.org/10.1109/iscas.2008.4542064","title":"Design and realization of continuous-time wave digital filters","display_name":"Design and realization of continuous-time wave digital filters","publication_year":2008,"publication_date":"2008-05-01","ids":{"openalex":"https://openalex.org/W2167232675","doi":"https://doi.org/10.1109/iscas.2008.4542064","mag":"2167232675"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2008.4542064","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2008.4542064","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5005246658","display_name":"Dieter Br\u00fcckmann","orcid":null},"institutions":[{"id":"https://openalex.org/I167360494","display_name":"University of Wuppertal","ror":"https://ror.org/00613ak93","country_code":"DE","type":"education","lineage":["https://openalex.org/I167360494"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"Dieter Bruckmann","raw_affiliation_strings":["Faculty of Electrical, Information and Media Engineering, University of Wuppertal, Wuppertal, Germany"],"affiliations":[{"raw_affiliation_string":"Faculty of Electrical, Information and Media Engineering, University of Wuppertal, Wuppertal, Germany","institution_ids":["https://openalex.org/I167360494"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5005246658"],"corresponding_institution_ids":["https://openalex.org/I167360494"],"apc_list":null,"apc_paid":null,"fwci":2.986,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.91759777,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"39","issue":null,"first_page":"2901","last_page":"2904"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11034","display_name":"Digital Filter Design and Implementation","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9911999702453613,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/realization","display_name":"Realization (probability)","score":0.7125866413116455},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6700531244277954},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.5919657945632935},{"id":"https://openalex.org/keywords/digital-filter","display_name":"Digital filter","score":0.5849122405052185},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5010385513305664},{"id":"https://openalex.org/keywords/filter","display_name":"Filter (signal processing)","score":0.4961477220058441},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.4880896806716919},{"id":"https://openalex.org/keywords/noise","display_name":"Noise (video)","score":0.45925185084342957},{"id":"https://openalex.org/keywords/digital-delay-line","display_name":"Digital delay line","score":0.4468124508857727},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.21129140257835388},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.16295772790908813},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.12205097079277039}],"concepts":[{"id":"https://openalex.org/C2781089630","wikidata":"https://www.wikidata.org/wiki/Q21856745","display_name":"Realization (probability)","level":2,"score":0.7125866413116455},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6700531244277954},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.5919657945632935},{"id":"https://openalex.org/C36390408","wikidata":"https://www.wikidata.org/wiki/Q1163067","display_name":"Digital filter","level":3,"score":0.5849122405052185},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5010385513305664},{"id":"https://openalex.org/C106131492","wikidata":"https://www.wikidata.org/wiki/Q3072260","display_name":"Filter (signal processing)","level":2,"score":0.4961477220058441},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.4880896806716919},{"id":"https://openalex.org/C99498987","wikidata":"https://www.wikidata.org/wiki/Q2210247","display_name":"Noise (video)","level":3,"score":0.45925185084342957},{"id":"https://openalex.org/C30847790","wikidata":"https://www.wikidata.org/wiki/Q4505961","display_name":"Digital delay line","level":4,"score":0.4468124508857727},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.21129140257835388},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16295772790908813},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.12205097079277039},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C31972630","wikidata":"https://www.wikidata.org/wiki/Q844240","display_name":"Computer vision","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2008.4542064","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2008.4542064","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1972580129","https://openalex.org/W2071013649","https://openalex.org/W2077011642","https://openalex.org/W2105936802","https://openalex.org/W2124153987","https://openalex.org/W2130220387","https://openalex.org/W2131554460","https://openalex.org/W2157685184","https://openalex.org/W2562527893","https://openalex.org/W4285719527"],"related_works":["https://openalex.org/W2909336477","https://openalex.org/W2015065719","https://openalex.org/W2072029011","https://openalex.org/W2403080104","https://openalex.org/W2029136999","https://openalex.org/W1986086798","https://openalex.org/W2351694994","https://openalex.org/W2020208026","https://openalex.org/W2109942901","https://openalex.org/W2375791940"],"abstract_inverted_index":{"Digital":[0],"signal":[1],"processing":[2],"in":[3,7,62,155],"continuous-time":[4,85,137],"can":[5,116],"result":[6],"a":[8,39,54,69,111,120,127,144,151],"number":[9,71,122,145],"of":[10,22,42,48,72,84,123,146],"advantages":[11,21,147],"compared":[12],"to":[13,27,76,104,140],"classical":[14],"sampled":[15,63],"data":[16,64],"systems,":[17],"while":[18],"the":[19,46,49,60,82,141],"inherent":[20],"digital":[23,87],"implementations":[24],"with":[25,68,102,119],"respect":[26,103],"programmability":[28],"and":[29,106,150],"noise":[30],"immunity":[31],"are":[32,148],"retained.":[33],"It":[34],"turned":[35],"out":[36],"however":[37],"that":[38],"critical":[40],"point":[41],"these":[43],"systems":[44],"is":[45,90,95],"implementation":[47,83],"continuous-":[50],"time":[51],"delays,":[52],"requiring":[53],"considerably":[55],"larger":[56],"chip":[57],"area":[58],"than":[59],"delays":[61],"systems.":[65],"Thus":[66],"structures":[67],"minimum":[70,121],"delay":[73,124],"elements":[74,125],"seem":[75],"be":[77,117],"advantageous.":[78],"In":[79],"this":[80],"contribution":[81],"wave":[86],"filters":[88],"(WDFs)":[89],"considered.":[91],"This":[92],"filter":[93,129],"type":[94],"well-":[96],"known":[97],"for":[98,126,136],"its":[99],"superior":[100],"properties":[101],"stability":[105],"sensitivity.":[107],"Furthermore,":[108],"by":[109],"selecting":[110],"proper":[112],"reference":[113],"structure,":[114],"WDFs":[115],"implemented":[118],"given":[128],"specification":[130],"thus":[131],"making":[132],"them":[133],"very":[134,152],"attractive":[135],"implementations.":[138],"Due":[139],"proposed":[142],"concept":[143],"obtained":[149],"efficient":[153],"realization":[154],"VLSI-technology":[156],"becomes":[157],"feasible.":[158]},"counts_by_year":[{"year":2014,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
