{"id":"https://openalex.org/W2137077125","doi":"https://doi.org/10.1109/iscas.2008.4541842","title":"Logic synthesis method for FPGAs with embedded memory blocks","display_name":"Logic synthesis method for FPGAs with embedded memory blocks","publication_year":2008,"publication_date":"2008-05-01","ids":{"openalex":"https://openalex.org/W2137077125","doi":"https://doi.org/10.1109/iscas.2008.4541842","mag":"2137077125"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2008.4541842","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2008.4541842","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5066021472","display_name":"Mariusz Rawski","orcid":"https://orcid.org/0000-0002-7489-0785"},"institutions":[{"id":"https://openalex.org/I108403487","display_name":"Warsaw University of Technology","ror":"https://ror.org/00y0xnp53","country_code":"PL","type":"education","lineage":["https://openalex.org/I108403487"]}],"countries":["PL"],"is_corresponding":false,"raw_author_name":"Mariusz Rawski","raw_affiliation_strings":["Institute of Telecommunications, Warsaw University of Technology, Warsaw, Poland","Inst. of Telecommun., Warsaw Univ. of Technol., Warsaw"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Telecommunications, Warsaw University of Technology, Warsaw, Poland","institution_ids":["https://openalex.org/I108403487"]},{"raw_affiliation_string":"Inst. of Telecommun., Warsaw Univ. of Technol., Warsaw","institution_ids":["https://openalex.org/I108403487"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5016478346","display_name":"B.J. Falkowski","orcid":null},"institutions":[{"id":"https://openalex.org/I172675005","display_name":"Nanyang Technological University","ror":"https://ror.org/02e7b5302","country_code":"SG","type":"education","lineage":["https://openalex.org/I172675005"]}],"countries":["SG"],"is_corresponding":false,"raw_author_name":"Bogdan J. Falkowski","raw_affiliation_strings":["School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore","Nanyang Technological University, School of Electrical and Electronic Engineering, 639798, Singapore"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore","institution_ids":["https://openalex.org/I172675005"]},{"raw_affiliation_string":"Nanyang Technological University, School of Electrical and Electronic Engineering, 639798, Singapore","institution_ids":["https://openalex.org/I172675005"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5051919904","display_name":"Tadeusz \u0141uba","orcid":"https://orcid.org/0000-0002-4965-7842"},"institutions":[{"id":"https://openalex.org/I108403487","display_name":"Warsaw University of Technology","ror":"https://ror.org/00y0xnp53","country_code":"PL","type":"education","lineage":["https://openalex.org/I108403487"]}],"countries":["PL"],"is_corresponding":false,"raw_author_name":"Tadeusz Luba","raw_affiliation_strings":["Institute of Telecommunications, Warsaw University of Technology, Warsaw, Poland","Inst. of Telecommun., Warsaw Univ. of Technol., Warsaw"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute of Telecommunications, Warsaw University of Technology, Warsaw, Poland","institution_ids":["https://openalex.org/I108403487"]},{"raw_affiliation_string":"Inst. of Telecommun., Warsaw Univ. of Technol., Warsaw","institution_ids":["https://openalex.org/I108403487"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.0261,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.81313712,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"9","issue":null,"first_page":"2014","last_page":"2017"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9961000084877014,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9929999709129333,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8157223463058472},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7647256851196289},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6138873100280762},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.5512413382530212},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.5288411378860474},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.47212013602256775},{"id":"https://openalex.org/keywords/programmable-logic-device","display_name":"Programmable logic device","score":0.4411693215370178},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4305761456489563},{"id":"https://openalex.org/keywords/logic-block","display_name":"Logic block","score":0.42327409982681274},{"id":"https://openalex.org/keywords/logic-optimization","display_name":"Logic optimization","score":0.41099220514297485},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3783227205276489},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.15809917449951172},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.14504191279411316}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8157223463058472},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7647256851196289},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6138873100280762},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.5512413382530212},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.5288411378860474},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.47212013602256775},{"id":"https://openalex.org/C206274596","wikidata":"https://www.wikidata.org/wiki/Q1063837","display_name":"Programmable logic device","level":2,"score":0.4411693215370178},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4305761456489563},{"id":"https://openalex.org/C2778325283","wikidata":"https://www.wikidata.org/wiki/Q1125244","display_name":"Logic block","level":3,"score":0.42327409982681274},{"id":"https://openalex.org/C28449271","wikidata":"https://www.wikidata.org/wiki/Q6667469","display_name":"Logic optimization","level":4,"score":0.41099220514297485},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3783227205276489},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.15809917449951172},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.14504191279411316}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2008.4541842","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2008.4541842","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1544620635","https://openalex.org/W1579750695","https://openalex.org/W1969802502","https://openalex.org/W2041871970","https://openalex.org/W2142508560","https://openalex.org/W2150387961","https://openalex.org/W6632451215"],"related_works":["https://openalex.org/W2135636985","https://openalex.org/W1966764473","https://openalex.org/W2139569078","https://openalex.org/W4252227487","https://openalex.org/W2063686821","https://openalex.org/W4252906329","https://openalex.org/W2170504327","https://openalex.org/W2171679639","https://openalex.org/W2151927748","https://openalex.org/W2139206565"],"abstract_inverted_index":{"The":[0,31],"paper":[1],"presents":[2],"a":[3],"logic":[4],"synthesis":[5],"method":[6],"oriented":[7],"towards":[8],"FPGA":[9,49],"architectures":[10],"with":[11],"specialized":[12,28],"embedded":[13,29],"memory":[14],"blocks.":[15],"Existing":[16],"methods":[17],"do":[18],"not":[19],"ensure":[20],"effective":[21,42],"utilization":[22],"of":[23,44],"possibilities":[24],"provided":[25],"by":[26],"these":[27],"modules.":[30],"presented":[32],"method,":[33],"based":[34],"on":[35],"balanced":[36],"decomposition,":[37],"leads":[38],"to":[39],"much":[40],"more":[41],"implementations":[43],"digital":[45],"systems":[46],"in":[47],"modern":[48],"structures.":[50]},"counts_by_year":[{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
