{"id":"https://openalex.org/W2142423500","doi":"https://doi.org/10.1109/iscas.2008.4541676","title":"HAFT: A hybrid FPGA with amorphous and fault-tolerant architecture","display_name":"HAFT: A hybrid FPGA with amorphous and fault-tolerant architecture","publication_year":2008,"publication_date":"2008-05-01","ids":{"openalex":"https://openalex.org/W2142423500","doi":"https://doi.org/10.1109/iscas.2008.4541676","mag":"2142423500"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2008.4541676","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2008.4541676","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5060908808","display_name":"Mingjie Lin","orcid":"https://orcid.org/0000-0002-3225-4406"},"institutions":[{"id":"https://openalex.org/I97018004","display_name":"Stanford University","ror":"https://ror.org/00f54p054","country_code":"US","type":"education","lineage":["https://openalex.org/I97018004"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mingjie Lin","raw_affiliation_strings":["Electrical Engineering Department at Stanford University, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical Engineering Department at Stanford University, USA","institution_ids":["https://openalex.org/I97018004"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102156506","display_name":"Steve Ferguson","orcid":null},"institutions":[{"id":"https://openalex.org/I97018004","display_name":"Stanford University","ror":"https://ror.org/00f54p054","country_code":"US","type":"education","lineage":["https://openalex.org/I97018004"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Steve Ferguson","raw_affiliation_strings":["Electrical Engineering Department at Stanford University, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical Engineering Department at Stanford University, USA","institution_ids":["https://openalex.org/I97018004"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5082418456","display_name":"Yaling Ma","orcid":null},"institutions":[{"id":"https://openalex.org/I97018004","display_name":"Stanford University","ror":"https://ror.org/00f54p054","country_code":"US","type":"education","lineage":["https://openalex.org/I97018004"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Yaling Ma","raw_affiliation_strings":["Electrical Engineering Department at Stanford University, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical Engineering Department at Stanford University, USA","institution_ids":["https://openalex.org/I97018004"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5014231039","display_name":"Timothy Greene","orcid":null},"institutions":[{"id":"https://openalex.org/I97018004","display_name":"Stanford University","ror":"https://ror.org/00f54p054","country_code":"US","type":"education","lineage":["https://openalex.org/I97018004"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Timothy Greene","raw_affiliation_strings":["Electrical Engineering Department at Stanford University, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical Engineering Department at Stanford University, USA","institution_ids":["https://openalex.org/I97018004"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I97018004"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.24074676,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"6","issue":null,"first_page":"1348","last_page":"1351"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/crossbar-switch","display_name":"Crossbar switch","score":0.8407319188117981},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6763569116592407},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5940529704093933},{"id":"https://openalex.org/keywords/routing","display_name":"Routing (electronic design automation)","score":0.5662227869033813},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5261649489402771},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.4458266496658325},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.43216472864151},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.4225667715072632},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.39603736996650696},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3772740066051483},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3335208296775818},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.18650290369987488}],"concepts":[{"id":"https://openalex.org/C29984679","wikidata":"https://www.wikidata.org/wiki/Q1929149","display_name":"Crossbar switch","level":2,"score":0.8407319188117981},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6763569116592407},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5940529704093933},{"id":"https://openalex.org/C74172769","wikidata":"https://www.wikidata.org/wiki/Q1446839","display_name":"Routing (electronic design automation)","level":2,"score":0.5662227869033813},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5261649489402771},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.4458266496658325},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.43216472864151},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.4225667715072632},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.39603736996650696},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3772740066051483},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3335208296775818},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.18650290369987488},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2008.4541676","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2008.4541676","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W2007049691","https://openalex.org/W2014286544","https://openalex.org/W2045617353","https://openalex.org/W2088859456","https://openalex.org/W2111173832","https://openalex.org/W2139637699","https://openalex.org/W2140055763","https://openalex.org/W2147004330","https://openalex.org/W2154941994"],"related_works":["https://openalex.org/W1966764473","https://openalex.org/W2098419840","https://openalex.org/W2526300902","https://openalex.org/W2121963733","https://openalex.org/W1977171228","https://openalex.org/W2170504327","https://openalex.org/W4249951793","https://openalex.org/W1990901299","https://openalex.org/W2789349722","https://openalex.org/W2041787842"],"abstract_inverted_index":{"We":[0],"propose":[1],"a":[2,7,74,106],"hybrid":[3,40,155],"FPGA":[4,41,99,156],"architecture":[5,20,103],"with":[6,83,100,136],"dense":[8],"and":[9,27,33,55,65,73,118,160,166],"defective":[10],"nano-crossbar":[11],"serving":[12],"as":[13,61],"its":[14,161],"configuration":[15],"memory.":[16,140],"An":[17],"amorphous":[18],"routing":[19,28,77],"is":[21,42],"adopted":[22],"to":[23,34,44,52,57,81,152],"optimally":[24],"allocate":[25],"logic":[26,37,63,110,164],"resource":[29],"on":[30],"per-mapping":[31],"basis":[32],"achieve":[35,105],"high":[36],"density.":[38],"This":[39],"designed":[43,80],"be":[45],"efficient":[46],"in":[47,95,109,114,121,146,163],"using":[48],"nano-crosspoints,":[49],"highly":[50],"tolerant":[51],"memory":[53,148],"defects,":[54],"versatile":[56],"provide":[58],"features":[59,87],"such":[60],"variable-granularity":[62],"blocks":[64],"variable-length":[66],"bypassing":[67],"interconnects.":[68],"A":[69],"new":[70],"placement":[71],"algorithm":[72],"modified":[75],"delay-based":[76],"procedure":[78],"are":[79],"match":[82],"many":[84],"unconventional":[85],"architectural":[86],"of":[88,144],"the":[89,96,101,122,126,137,142,147],"proposed":[90,102],"FPGA.":[91],"Assuming":[92],"zero":[93],"defect-rate":[94],"nano-crossbar,":[97],"an":[98,133],"can":[104],"30%":[107],"improvement":[108,113,120,162],"density,":[111],"12%":[112],"average":[115],"net":[116],"delay,":[117],"8%":[119],"critical-path":[123],"delay":[124,167],"for":[125],"largest":[127],"20":[128],"MCNC":[129],"benchmark":[130],"circuits":[131],"over":[132],"island-style":[134],"baseline":[135],"same":[138],"nano-scale":[139],"As":[141],"rate":[143],"defects":[145],"increases":[149],"from":[150],"0%":[151],"50%,":[153],"this":[154],"remains":[157],"fully":[158],"functional":[159],"density":[165],"performance":[168],"only":[169],"drops":[170],"by":[171],"approximately":[172],"23%.":[173]},"counts_by_year":[{"year":2016,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}