{"id":"https://openalex.org/W2104172238","doi":"https://doi.org/10.1109/iscas.2008.4541487","title":"High speed digital CMOS divide-by-N fequency divider","display_name":"High speed digital CMOS divide-by-N fequency divider","publication_year":2008,"publication_date":"2008-05-01","ids":{"openalex":"https://openalex.org/W2104172238","doi":"https://doi.org/10.1109/iscas.2008.4541487","mag":"2104172238"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2008.4541487","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2008.4541487","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5091004171","display_name":"Saleh Abdel\u2010hafeez","orcid":"https://orcid.org/0000-0003-2988-1609"},"institutions":[{"id":"https://openalex.org/I156983542","display_name":"Jordan University of Science and Technology","ror":"https://ror.org/03y8mtb59","country_code":"JO","type":"education","lineage":["https://openalex.org/I156983542"]}],"countries":["JO"],"is_corresponding":false,"raw_author_name":"Saleh Abdel-Hafeez","raw_affiliation_strings":["Department of Computer Engineering, Jordan University of Science & Technology, Irbid, 21110 Jordan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Computer Engineering, Jordan University of Science & Technology, Irbid, 21110 Jordan","institution_ids":["https://openalex.org/I156983542"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5034033798","display_name":"Shadi M. Harb","orcid":"https://orcid.org/0000-0001-8146-2837"},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Shadi M. Harb","raw_affiliation_strings":["Electrical & Computer Engineering Department, University of Florida, Gainesville, 32611, USA","Electrical and Computer Engineering Department, University of Florida, Gainesville 32611, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical & Computer Engineering Department, University of Florida, Gainesville, 32611, USA","institution_ids":["https://openalex.org/I33213144"]},{"raw_affiliation_string":"Electrical and Computer Engineering Department, University of Florida, Gainesville 32611, USA","institution_ids":["https://openalex.org/I33213144"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5061760483","display_name":"W.R. Eisenstadt","orcid":"https://orcid.org/0000-0003-2920-6638"},"institutions":[{"id":"https://openalex.org/I33213144","display_name":"University of Florida","ror":"https://ror.org/02y3ad647","country_code":"US","type":"education","lineage":["https://openalex.org/I33213144"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"William R. Eisenstadt","raw_affiliation_strings":["Electrical & Computer Engineering Department, University of Florida, Gainesville, 32611, USA","Electrical and Computer Engineering Department, University of Florida, Gainesville 32611, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Electrical & Computer Engineering Department, University of Florida, Gainesville, 32611, USA","institution_ids":["https://openalex.org/I33213144"]},{"raw_affiliation_string":"Electrical and Computer Engineering Department, University of Florida, Gainesville 32611, USA","institution_ids":["https://openalex.org/I33213144"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.0175,"has_fulltext":false,"cited_by_count":18,"citation_normalized_percentile":{"value":0.78601821,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"592","last_page":"595"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/frequency-divider","display_name":"Frequency divider","score":0.7278839945793152},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6505691409111023},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.5760191679000854},{"id":"https://openalex.org/keywords/voltage-divider","display_name":"Voltage divider","score":0.5122522711753845},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.4893002212047577},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.481579065322876},{"id":"https://openalex.org/keywords/signal-edge","display_name":"Signal edge","score":0.4598376154899597},{"id":"https://openalex.org/keywords/flip-flop","display_name":"Flip-flop","score":0.45081764459609985},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.43197423219680786},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3829447329044342},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.3379107117652893},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.27599865198135376}],"concepts":[{"id":"https://openalex.org/C74982907","wikidata":"https://www.wikidata.org/wiki/Q1455624","display_name":"Frequency divider","level":3,"score":0.7278839945793152},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6505691409111023},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.5760191679000854},{"id":"https://openalex.org/C49324399","wikidata":"https://www.wikidata.org/wiki/Q466758","display_name":"Voltage divider","level":3,"score":0.5122522711753845},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.4893002212047577},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.481579065322876},{"id":"https://openalex.org/C117525741","wikidata":"https://www.wikidata.org/wiki/Q775654","display_name":"Signal edge","level":4,"score":0.4598376154899597},{"id":"https://openalex.org/C2781007278","wikidata":"https://www.wikidata.org/wiki/Q183406","display_name":"Flip-flop","level":3,"score":0.45081764459609985},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.43197423219680786},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3829447329044342},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.3379107117652893},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.27599865198135376},{"id":"https://openalex.org/C13412647","wikidata":"https://www.wikidata.org/wiki/Q174948","display_name":"Analog signal","level":3,"score":0.0},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2008.4541487","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2008.4541487","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8799999952316284,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W1489200271","https://openalex.org/W1517657880","https://openalex.org/W1528493849","https://openalex.org/W1570624637","https://openalex.org/W1876414689","https://openalex.org/W1982801875","https://openalex.org/W2026861460","https://openalex.org/W2045704342","https://openalex.org/W2053214475","https://openalex.org/W2061152750","https://openalex.org/W2071573095","https://openalex.org/W2093559139","https://openalex.org/W2109195618","https://openalex.org/W2115581704","https://openalex.org/W2139625690","https://openalex.org/W2151254061","https://openalex.org/W2154502576","https://openalex.org/W2156815834","https://openalex.org/W2788994943","https://openalex.org/W6639374216"],"related_works":["https://openalex.org/W2786631194","https://openalex.org/W2051658160","https://openalex.org/W2019303688","https://openalex.org/W2613801068","https://openalex.org/W2607268936","https://openalex.org/W2121476578","https://openalex.org/W2602267976","https://openalex.org/W2149388434","https://openalex.org/W2125493782","https://openalex.org/W1967412649"],"abstract_inverted_index":{"A":[0],"high-speed":[1],"scalable":[2],"programmable":[3,180],"divide-by-N":[4,181],"frequency":[5,182,210],"divider":[6,10,75,118,123,175,183,211],"is":[7,29,56,66,80,84,125,134,160,184],"presented.":[8],"The":[9,27,53,73,152,177],"includes":[11],"a":[12,20,57,69,92,97,104,163,170,193,200,208,225,235],"new":[13],"proposed":[14],"state":[15],"look-ahead":[16],"parallel":[17],"counter":[18,28,36],"with":[19,146,199,234],"basic":[21],"conventional":[22],"D-type":[23],"Flip-Flop":[24],"(DFF)":[25],"circuit.":[26],"structured":[30],"from":[31,68],"two":[32,70],"modules":[33,139],"of":[34,49,82,91,116,140,143,155,158,166,173,186,204,213,228,238],"2-bit":[35],"stages":[37],"separated":[38],"by":[39],"DFF":[40,59],"buffers,":[41],"where":[42],"all":[43],"are":[44],"triggered":[45],"at":[46],"the":[47,50,62,114,117,122,132,156,174,216],"edge":[48],"input":[51],"clock.":[52],"reload":[54],"circuit":[55,65,124],"single":[58],"buffer,":[60],"while":[61],"detecting":[63],"count":[64,142,237],"constructed":[67],"level":[71],"decoder.":[72],"M-bit":[74],"critical":[76],"path":[77],"delay,":[78],"which":[79,107],"independent":[81],"technology,":[83],"approximated":[85,161],"to":[86,96,110,162,189],"[3.5":[87],"+":[88],"Log4":[89],"(M)]":[90],"unit":[93],"delay":[94],"close":[95],"2-input":[98],"NAND":[99],"gate.":[100],"This":[101],"results":[102],"in":[103],"measured":[105,226],"frequency,":[106],"slightly":[108],"drops":[109],"about":[111,167],"6%":[112],"against":[113],"increase":[115,165,172],"bit":[119],"size.":[120,176],"Furthermore,":[121],"attractive":[126],"for":[127,192],"continued":[128],"technology":[129,150],"scaling":[130],"since":[131],"architecture":[133],"based":[135],"on":[136],"using":[137,215],"identical":[138],"small":[141],"CMOS":[144,221],"transistors":[145,159],"only":[147],"threshold":[148],"voltage":[149,198],"limitations.":[151],"measure":[153],"rate":[154],"number":[157],"linear":[164],"17%":[168],"per":[169],"two-bit":[171],"presented":[178],"8-bit":[179],"capable":[185],"operating":[187],"up":[188],"2":[190],"GHz":[191],"1.35":[194],"V":[195],"power":[196,202],"supply":[197],"maximum":[201,209],"consumption":[203],"16.78":[205],"mW":[206],"and":[207,223],"factor":[212],"N=256":[214],"TSMC":[217],"0.15":[218],"mum":[219,230],"digital":[220],"process,":[222],"gives":[224],"area":[227],"95*143":[229],"<sup":[231],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[232],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[233],"total":[236],"508":[239],"transistors.":[240]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":4},{"year":2023,"cited_by_count":2},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2012,"cited_by_count":2}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}