{"id":"https://openalex.org/W2098776782","doi":"https://doi.org/10.1109/iscas.2008.4541484","title":"A Dual-Vt low leakage SRAM array robust to process variations","display_name":"A Dual-Vt low leakage SRAM array robust to process variations","publication_year":2008,"publication_date":"2008-05-01","ids":{"openalex":"https://openalex.org/W2098776782","doi":"https://doi.org/10.1109/iscas.2008.4541484","mag":"2098776782"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2008.4541484","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2008.4541484","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5035555716","display_name":"Jungseob Lee","orcid":"https://orcid.org/0000-0002-9431-6342"},"institutions":[{"id":"https://openalex.org/I135310074","display_name":"University of Wisconsin\u2013Madison","ror":"https://ror.org/01y2jtd41","country_code":"US","type":"education","lineage":["https://openalex.org/I135310074"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jungseob Lee","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Wisconsin at Madison, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Wisconsin at Madison, USA","institution_ids":["https://openalex.org/I135310074"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101549412","display_name":"Lin Xie","orcid":"https://orcid.org/0000-0001-5385-7380"},"institutions":[{"id":"https://openalex.org/I135310074","display_name":"University of Wisconsin\u2013Madison","ror":"https://ror.org/01y2jtd41","country_code":"US","type":"education","lineage":["https://openalex.org/I135310074"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Lin Xie","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Wisconsin at Madison, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Wisconsin at Madison, USA","institution_ids":["https://openalex.org/I135310074"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5072204999","display_name":"Azadeh Davoodi","orcid":"https://orcid.org/0000-0001-5213-2556"},"institutions":[{"id":"https://openalex.org/I135310074","display_name":"University of Wisconsin\u2013Madison","ror":"https://ror.org/01y2jtd41","country_code":"US","type":"education","lineage":["https://openalex.org/I135310074"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Azadeh Davoodi","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Wisconsin at Madison, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Wisconsin at Madison, USA","institution_ids":["https://openalex.org/I135310074"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.3567,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.82090585,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"580","last_page":"583"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.6350041031837463},{"id":"https://openalex.org/keywords/dual","display_name":"Dual (grammatical number)","score":0.6223185658454895},{"id":"https://openalex.org/keywords/leakage","display_name":"Leakage (economics)","score":0.5530048608779907},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5477131009101868},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.47237613797187805},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.44507747888565063},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2043757438659668},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.0643576979637146}],"concepts":[{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.6350041031837463},{"id":"https://openalex.org/C2780980858","wikidata":"https://www.wikidata.org/wiki/Q110022","display_name":"Dual (grammatical number)","level":2,"score":0.6223185658454895},{"id":"https://openalex.org/C2777042071","wikidata":"https://www.wikidata.org/wiki/Q6509304","display_name":"Leakage (economics)","level":2,"score":0.5530048608779907},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5477131009101868},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.47237613797187805},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.44507747888565063},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2043757438659668},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0643576979637146},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C124952713","wikidata":"https://www.wikidata.org/wiki/Q8242","display_name":"Literature","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2008.4541484","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2008.4541484","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE International Symposium on Circuits and Systems (ISCAS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1589130434","https://openalex.org/W2095754833","https://openalex.org/W2095776198","https://openalex.org/W2099911327","https://openalex.org/W2107461595","https://openalex.org/W2109220580","https://openalex.org/W2119465663","https://openalex.org/W2123009614","https://openalex.org/W2135956512","https://openalex.org/W2161524358","https://openalex.org/W2172020468","https://openalex.org/W6677843167"],"related_works":["https://openalex.org/W4392590355","https://openalex.org/W3151633427","https://openalex.org/W2212894501","https://openalex.org/W2793465010","https://openalex.org/W3024050170","https://openalex.org/W1976168335","https://openalex.org/W2109451123","https://openalex.org/W2051487156","https://openalex.org/W4378977321","https://openalex.org/W3211992815"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,19,38,49,57,86],"dual-V":[4,25],"<sub":[5,26],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[6,27],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">t</sub>":[7,28],"SRAM":[8,45],"array":[9,46],"design":[10],"which":[11,36,67],"is":[12,34,93],"robust":[13],"to":[14,22,40,47],"process":[15],"variations.":[16],"After":[17],"reviewing":[18],"cell-level":[20],"analysis":[21],"compare":[23],"various":[24,91],"configurations":[29],"under":[30],"variations,":[31],"an":[32,44],"algorithm":[33,64],"introduced":[35],"assigns":[37],"configuration":[39],"each":[41],"cell":[42],"in":[43,71],"meet":[48],"target":[50,87],"read":[51,88],"delay":[52,73,89],"with":[53,75],"minimum":[54],"leakage":[55],"at":[56,90,94],"desired":[58],"probability.":[59],"Two":[60],"versions":[61],"of":[62,77,84],"the":[63,82],"are":[65],"discussed":[66],"trade":[68],"off":[69],"accuracy":[70],"wire":[72],"estimation":[74],"granularity":[76],"assignment.":[78],"Simulation":[79],"results":[80],"show":[81],"probability":[83],"meeting":[85],"locations":[92],"least":[95],"0.93":[96],"using":[97],"our":[98],"proposed":[99],"techniques.":[100]},"counts_by_year":[{"year":2013,"cited_by_count":2}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}