{"id":"https://openalex.org/W2156779163","doi":"https://doi.org/10.1109/iscas.2006.1693938","title":"Analog frequency response measurement in mixed-signal systems","display_name":"Analog frequency response measurement in mixed-signal systems","publication_year":2006,"publication_date":"2006-09-22","ids":{"openalex":"https://openalex.org/W2156779163","doi":"https://doi.org/10.1109/iscas.2006.1693938","mag":"2156779163"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2006.1693938","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2006.1693938","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5033039433","display_name":"Charles E. Stroud","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"C. Stroud","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Aubum University, AL, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Aubum University, AL, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019206025","display_name":"Dayu Yang","orcid":"https://orcid.org/0000-0002-5811-5690"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Dayu Yang","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Aubum University, AL, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Aubum University, AL, USA","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5035165376","display_name":"Fa Foster Dai","orcid":"https://orcid.org/0000-0003-1691-6649"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"F. Dai","raw_affiliation_strings":["Department of Electrical and Computer Engineering, Aubum University, AL, USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, Aubum University, AL, USA","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5033039433"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.5044,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.84013118,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"4","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9952999949455261,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.6057232022285461},{"id":"https://openalex.org/keywords/linearity","display_name":"Linearity","score":0.5726128220558167},{"id":"https://openalex.org/keywords/frequency-response","display_name":"Frequency response","score":0.5514543652534485},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5488659739494324},{"id":"https://openalex.org/keywords/mixed-signal-integrated-circuit","display_name":"Mixed-signal integrated circuit","score":0.5403270125389099},{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.5201104879379272},{"id":"https://openalex.org/keywords/frequency-multiplier","display_name":"Frequency multiplier","score":0.48787474632263184},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.48577526211738586},{"id":"https://openalex.org/keywords/analog-multiplier","display_name":"Analog multiplier","score":0.45779305696487427},{"id":"https://openalex.org/keywords/sine-wave","display_name":"Sine wave","score":0.45157590508461},{"id":"https://openalex.org/keywords/signal","display_name":"SIGNAL (programming language)","score":0.43575966358184814},{"id":"https://openalex.org/keywords/direct-digital-synthesizer","display_name":"Direct digital synthesizer","score":0.42099612951278687},{"id":"https://openalex.org/keywords/analog-signal-processing","display_name":"Analog signal processing","score":0.41681474447250366},{"id":"https://openalex.org/keywords/analog-signal","display_name":"Analog signal","score":0.39230501651763916},{"id":"https://openalex.org/keywords/frequency-synthesizer","display_name":"Frequency synthesizer","score":0.35051366686820984},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.32605552673339844},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.27606475353240967},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.2676316499710083},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2502705454826355},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.24381718039512634},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.22775119543075562},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.1760074496269226},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.12198853492736816},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.1053304374217987}],"concepts":[{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.6057232022285461},{"id":"https://openalex.org/C77170095","wikidata":"https://www.wikidata.org/wiki/Q1753188","display_name":"Linearity","level":2,"score":0.5726128220558167},{"id":"https://openalex.org/C8590192","wikidata":"https://www.wikidata.org/wiki/Q1054694","display_name":"Frequency response","level":2,"score":0.5514543652534485},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5488659739494324},{"id":"https://openalex.org/C62907940","wikidata":"https://www.wikidata.org/wiki/Q1541329","display_name":"Mixed-signal integrated circuit","level":3,"score":0.5403270125389099},{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.5201104879379272},{"id":"https://openalex.org/C146002875","wikidata":"https://www.wikidata.org/wiki/Q1074289","display_name":"Frequency multiplier","level":3,"score":0.48787474632263184},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.48577526211738586},{"id":"https://openalex.org/C98142538","wikidata":"https://www.wikidata.org/wiki/Q485005","display_name":"Analog multiplier","level":4,"score":0.45779305696487427},{"id":"https://openalex.org/C66907618","wikidata":"https://www.wikidata.org/wiki/Q207527","display_name":"Sine wave","level":3,"score":0.45157590508461},{"id":"https://openalex.org/C2779843651","wikidata":"https://www.wikidata.org/wiki/Q7390335","display_name":"SIGNAL (programming language)","level":2,"score":0.43575966358184814},{"id":"https://openalex.org/C166089067","wikidata":"https://www.wikidata.org/wiki/Q1227465","display_name":"Direct digital synthesizer","level":5,"score":0.42099612951278687},{"id":"https://openalex.org/C379707","wikidata":"https://www.wikidata.org/wiki/Q2328303","display_name":"Analog signal processing","level":4,"score":0.41681474447250366},{"id":"https://openalex.org/C13412647","wikidata":"https://www.wikidata.org/wiki/Q174948","display_name":"Analog signal","level":3,"score":0.39230501651763916},{"id":"https://openalex.org/C182099602","wikidata":"https://www.wikidata.org/wiki/Q2660678","display_name":"Frequency synthesizer","level":4,"score":0.35051366686820984},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.32605552673339844},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.27606475353240967},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.2676316499710083},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2502705454826355},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.24381718039512634},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.22775119543075562},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.1760074496269226},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.12198853492736816},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.1053304374217987},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2006.1693938","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2006.1693938","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5699999928474426,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W1522599302","https://openalex.org/W2119042407","https://openalex.org/W2164817320","https://openalex.org/W3147832843"],"related_works":["https://openalex.org/W2093119242","https://openalex.org/W2769992427","https://openalex.org/W2178871507","https://openalex.org/W1967648323","https://openalex.org/W1498879985","https://openalex.org/W2563014579","https://openalex.org/W2085674059","https://openalex.org/W2116226449","https://openalex.org/W2568296580","https://openalex.org/W2169924428"],"abstract_inverted_index":{"We":[0],"present":[1],"an":[2,96],"efficient":[3],"approach":[4,21,76],"for":[5,63,91],"on-chip":[6],"frequency":[7,92],"response":[8,39,93],"measurement,":[9],"including":[10],"phase":[11,49],"and":[12,35,45,61,67,89],"gain,":[13],"of":[14,69,95],"analog":[15,71],"circuitry":[16],"in":[17,79,82],"mixed-signal":[18],"systems.":[19],"The":[20,37,47,75],"uses":[22],"direct":[23],"digital":[24],"synthesizer":[25],"(DDS)":[26],"to":[27,54],"supply":[28],"test":[29],"sine":[30],"waves":[31],"with":[32],"different":[33],"frequencies":[34],"phases.":[36],"output":[38],"is":[40,52],"analyzed":[41],"using":[42],"a":[43,83],"multiplier":[44],"accumulator.":[46],"resultant":[48],"delay":[50],"measurement":[51],"used":[53,90],"correct":[55],"other":[56],"measurements":[57,94],"such":[58],"as":[59],"gain":[60],"linearity":[62],"more":[64],"accurate":[65],"testing":[66],"characterization":[68],"the":[70],"circuit":[72],"under":[73,99],"test.":[74,100],"was":[77],"implemented":[78],"Verilog,":[80],"synthesized":[81],"field":[84],"programmable":[85],"gate":[86],"array":[87],"(FPGA),":[88],"actual":[97],"device":[98]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}