{"id":"https://openalex.org/W1890842762","doi":"https://doi.org/10.1109/iscas.2006.1693785","title":"Circuit sizing method under delay constraint","display_name":"Circuit sizing method under delay constraint","publication_year":2006,"publication_date":"2006-09-22","ids":{"openalex":"https://openalex.org/W1890842762","doi":"https://doi.org/10.1109/iscas.2006.1693785","mag":"1890842762"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2006.1693785","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2006.1693785","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5084931832","display_name":"Alexandre Verle","orcid":null},"institutions":[{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"government","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I19894307","display_name":"Universit\u00e9 de Montpellier","ror":"https://ror.org/051escj72","country_code":"FR","type":"education","lineage":["https://openalex.org/I19894307"]},{"id":"https://openalex.org/I4210101743","display_name":"Laboratoire d'Informatique, de Robotique et de Micro\u00e9lectronique de Montpellier","ror":"https://ror.org/013yean28","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I1326498283","https://openalex.org/I151295451","https://openalex.org/I19894307","https://openalex.org/I4210101743","https://openalex.org/I4210159245","https://openalex.org/I4405261681"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"A. Verle","raw_affiliation_strings":["LIRMM, UMR CNRS/Universite de Montpellier II, Montpellier, France","LIRMM, Univ. de Montpellier II, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"LIRMM, UMR CNRS/Universite de Montpellier II, Montpellier, France","institution_ids":["https://openalex.org/I19894307","https://openalex.org/I1294671590","https://openalex.org/I4210101743"]},{"raw_affiliation_string":"LIRMM, Univ. de Montpellier II, France","institution_ids":["https://openalex.org/I4210101743"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5026401172","display_name":"Alexis Landrault","orcid":null},"institutions":[{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"government","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I19894307","display_name":"Universit\u00e9 de Montpellier","ror":"https://ror.org/051escj72","country_code":"FR","type":"education","lineage":["https://openalex.org/I19894307"]},{"id":"https://openalex.org/I4210101743","display_name":"Laboratoire d'Informatique, de Robotique et de Micro\u00e9lectronique de Montpellier","ror":"https://ror.org/013yean28","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I1326498283","https://openalex.org/I151295451","https://openalex.org/I19894307","https://openalex.org/I4210101743","https://openalex.org/I4210159245","https://openalex.org/I4405261681"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"A. Landrault","raw_affiliation_strings":["LIRMM, UMR CNRS/Universite de Montpellier II, Montpellier, France","LIRMM, Univ. de Montpellier II, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"LIRMM, UMR CNRS/Universite de Montpellier II, Montpellier, France","institution_ids":["https://openalex.org/I19894307","https://openalex.org/I1294671590","https://openalex.org/I4210101743"]},{"raw_affiliation_string":"LIRMM, Univ. de Montpellier II, France","institution_ids":["https://openalex.org/I4210101743"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5015351510","display_name":"Philippe Maurine","orcid":"https://orcid.org/0000-0002-9706-5710"},"institutions":[{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"government","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I19894307","display_name":"Universit\u00e9 de Montpellier","ror":"https://ror.org/051escj72","country_code":"FR","type":"education","lineage":["https://openalex.org/I19894307"]},{"id":"https://openalex.org/I4210101743","display_name":"Laboratoire d'Informatique, de Robotique et de Micro\u00e9lectronique de Montpellier","ror":"https://ror.org/013yean28","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I1326498283","https://openalex.org/I151295451","https://openalex.org/I19894307","https://openalex.org/I4210101743","https://openalex.org/I4210159245","https://openalex.org/I4405261681"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"P. Maurine","raw_affiliation_strings":["LIRMM, UMR CNRS/Universite de Montpellier II, Montpellier, France","LIRMM, Univ. de Montpellier II, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"LIRMM, UMR CNRS/Universite de Montpellier II, Montpellier, France","institution_ids":["https://openalex.org/I19894307","https://openalex.org/I1294671590","https://openalex.org/I4210101743"]},{"raw_affiliation_string":"LIRMM, Univ. de Montpellier II, France","institution_ids":["https://openalex.org/I4210101743"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5108376202","display_name":"Nadine Az\u00e9mard","orcid":null},"institutions":[{"id":"https://openalex.org/I1294671590","display_name":"Centre National de la Recherche Scientifique","ror":"https://ror.org/02feahw73","country_code":"FR","type":"government","lineage":["https://openalex.org/I1294671590"]},{"id":"https://openalex.org/I19894307","display_name":"Universit\u00e9 de Montpellier","ror":"https://ror.org/051escj72","country_code":"FR","type":"education","lineage":["https://openalex.org/I19894307"]},{"id":"https://openalex.org/I4210101743","display_name":"Laboratoire d'Informatique, de Robotique et de Micro\u00e9lectronique de Montpellier","ror":"https://ror.org/013yean28","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I1326498283","https://openalex.org/I151295451","https://openalex.org/I19894307","https://openalex.org/I4210101743","https://openalex.org/I4210159245","https://openalex.org/I4405261681"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"N. Azemard","raw_affiliation_strings":["LIRMM, UMR CNRS/Universite de Montpellier II, Montpellier, France","LIRMM, Univ. de Montpellier II, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"LIRMM, UMR CNRS/Universite de Montpellier II, Montpellier, France","institution_ids":["https://openalex.org/I19894307","https://openalex.org/I1294671590","https://openalex.org/I4210101743"]},{"raw_affiliation_string":"LIRMM, Univ. de Montpellier II, France","institution_ids":["https://openalex.org/I4210101743"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":"152","issue":null,"first_page":"4","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/sizing","display_name":"Sizing","score":0.8907136917114258},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7342467904090881},{"id":"https://openalex.org/keywords/constraint","display_name":"Constraint (computer-aided design)","score":0.5086567997932434},{"id":"https://openalex.org/keywords/divergence","display_name":"Divergence (linguistics)","score":0.45146867632865906},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4500201940536499},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4495502710342407},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4321900010108948},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.36420542001724243},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1456213891506195},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.13249844312667847}],"concepts":[{"id":"https://openalex.org/C2777767291","wikidata":"https://www.wikidata.org/wiki/Q1080291","display_name":"Sizing","level":2,"score":0.8907136917114258},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7342467904090881},{"id":"https://openalex.org/C2776036281","wikidata":"https://www.wikidata.org/wiki/Q48769818","display_name":"Constraint (computer-aided design)","level":2,"score":0.5086567997932434},{"id":"https://openalex.org/C207390915","wikidata":"https://www.wikidata.org/wiki/Q1230525","display_name":"Divergence (linguistics)","level":2,"score":0.45146867632865906},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4500201940536499},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4495502710342407},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4321900010108948},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.36420542001724243},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1456213891506195},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.13249844312667847},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C41895202","wikidata":"https://www.wikidata.org/wiki/Q8162","display_name":"Linguistics","level":1,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iscas.2006.1693785","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2006.1693785","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},{"id":"pmh:oai:HAL:lirmm-00106911v1","is_oa":false,"landing_page_url":"https://hal-lirmm.ccsd.cnrs.fr/lirmm-00106911","pdf_url":null,"source":{"id":"https://openalex.org/S4306402512","display_name":"HAL (Le Centre pour la Communication Scientifique Directe)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1294671590","host_organization_name":"Centre National de la Recherche Scientifique","host_organization_lineage":["https://openalex.org/I1294671590"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"ISCAS: International Symposium on Circuits and Systems, May 2006, Island of Kos, Greece. pp.5123-5126, &#x27E8;10.1109/ISCAS.2006.1693785&#x27E9;","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure","score":0.41999998688697815}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":17,"referenced_works":["https://openalex.org/W1569550779","https://openalex.org/W1856100621","https://openalex.org/W2001233997","https://openalex.org/W2004055019","https://openalex.org/W2011434382","https://openalex.org/W2088115909","https://openalex.org/W2099825461","https://openalex.org/W2131729827","https://openalex.org/W2149622198","https://openalex.org/W2149661268","https://openalex.org/W2149663872","https://openalex.org/W2160521563","https://openalex.org/W2171325910","https://openalex.org/W4237297289","https://openalex.org/W4248577596","https://openalex.org/W6634336121","https://openalex.org/W6681763760"],"related_works":["https://openalex.org/W2375311683","https://openalex.org/W2366062860","https://openalex.org/W2373777250","https://openalex.org/W2353956655","https://openalex.org/W2020653254","https://openalex.org/W2010454064","https://openalex.org/W2352072014","https://openalex.org/W217279133","https://openalex.org/W2393487946","https://openalex.org/W2373310108"],"abstract_inverted_index":{"In":[0],"the":[1,5,25,51,62,80],"last":[2],"step":[3],"of":[4,19,27,48,82],"design":[6],"flow,":[7],"circuit":[8,40,67],"performance":[9,81],"optimization":[10],"is":[11,22,70],"a":[12,56,75],"difficult":[13],"task":[14],"to":[15,23,60],"realize.":[16],"The":[17],"goal":[18],"this":[20],"work":[21],"avoid":[24],"use":[26],"CPU":[28],"time":[29],"expensive":[30],"random":[31],"mathematical":[32],"methods,":[33],"by":[34,72],"defining":[35],"an":[36,88],"accurate":[37],"and":[38,45,91],"deterministic":[39],"sizing":[41,47],"protocol,":[42],"allowing":[43],"easy":[44],"fast":[46],"circuits":[49],"at":[50],"required":[52],"speed.":[53],"We":[54],"propose":[55],"coefficient":[57],"based":[58],"approach":[59],"solve":[61],"divergence":[63],"branch":[64],"problem":[65],"for":[66],"sizing.":[68],"Validation":[69],"given":[71],"comparing,":[73],"in":[74],"standard":[76],"180nm":[77],"CMOS":[78],"process,":[79],"different":[83],"ISCAS":[84],"benchmarks":[85],"sized":[86],"with":[87],"industrial":[89],"tool":[90],"following":[92],"our":[93],"methodology":[94]},"counts_by_year":[],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
