{"id":"https://openalex.org/W1927636319","doi":"https://doi.org/10.1109/iscas.2006.1693651","title":"Via Placement for Minimum Interconnect Delay in Three-Dimensional (3-D) Circuits","display_name":"Via Placement for Minimum Interconnect Delay in Three-Dimensional (3-D) Circuits","publication_year":2006,"publication_date":"2006-09-22","ids":{"openalex":"https://openalex.org/W1927636319","doi":"https://doi.org/10.1109/iscas.2006.1693651","mag":"1927636319"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2006.1693651","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2006.1693651","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5031542707","display_name":"Vasilis F. Pavlidis","orcid":"https://orcid.org/0000-0002-4063-4652"},"institutions":[{"id":"https://openalex.org/I5388228","display_name":"University of Rochester","ror":"https://ror.org/022kthw22","country_code":"US","type":"education","lineage":["https://openalex.org/I5388228"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"V.F. Pavlidis","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Rochester, Rochester, NY, USA","[Dept. of Electr. & Comput. Eng., Rochester Univ., NY, USA]"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Rochester, Rochester, NY, USA","institution_ids":["https://openalex.org/I5388228"]},{"raw_affiliation_string":"[Dept. of Electr. & Comput. Eng., Rochester Univ., NY, USA]","institution_ids":["https://openalex.org/I5388228"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5053517349","display_name":"Eby G. Friedman","orcid":"https://orcid.org/0000-0002-5549-7160"},"institutions":[{"id":"https://openalex.org/I5388228","display_name":"University of Rochester","ror":"https://ror.org/022kthw22","country_code":"US","type":"education","lineage":["https://openalex.org/I5388228"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"E.G. Friedman","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Rochester, Rochester, NY, USA","[Dept. of Electr. & Comput. Eng., Rochester Univ., NY, USA]"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Rochester, Rochester, NY, USA","institution_ids":["https://openalex.org/I5388228"]},{"raw_affiliation_string":"[Dept. of Electr. & Comput. Eng., Rochester Univ., NY, USA]","institution_ids":["https://openalex.org/I5388228"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5031542707"],"corresponding_institution_ids":["https://openalex.org/I5388228"],"apc_list":null,"apc_paid":null,"fwci":2.6806,"has_fulltext":false,"cited_by_count":13,"citation_normalized_percentile":{"value":0.89079614,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"4587","last_page":"4590"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/elmore-delay","display_name":"Elmore delay","score":0.9021425247192383},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.8330786228179932},{"id":"https://openalex.org/keywords/propagation-delay","display_name":"Propagation delay","score":0.792870044708252},{"id":"https://openalex.org/keywords/sizing","display_name":"Sizing","score":0.7279835343360901},{"id":"https://openalex.org/keywords/delay-calculation","display_name":"Delay calculation","score":0.6946298480033875},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5856767892837524},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5380593538284302},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.531457781791687},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.41679617762565613},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.3936634063720703},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.29243582487106323},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.25441688299179077},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.11838170886039734},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.11002177000045776}],"concepts":[{"id":"https://openalex.org/C84434228","wikidata":"https://www.wikidata.org/wiki/Q4531332","display_name":"Elmore delay","level":4,"score":0.9021425247192383},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.8330786228179932},{"id":"https://openalex.org/C90806461","wikidata":"https://www.wikidata.org/wiki/Q1144416","display_name":"Propagation delay","level":2,"score":0.792870044708252},{"id":"https://openalex.org/C2777767291","wikidata":"https://www.wikidata.org/wiki/Q1080291","display_name":"Sizing","level":2,"score":0.7279835343360901},{"id":"https://openalex.org/C174086752","wikidata":"https://www.wikidata.org/wiki/Q5253471","display_name":"Delay calculation","level":3,"score":0.6946298480033875},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5856767892837524},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5380593538284302},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.531457781791687},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.41679617762565613},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.3936634063720703},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.29243582487106323},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.25441688299179077},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.11838170886039734},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.11002177000045776},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/iscas.2006.1693651","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2006.1693651","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},{"id":"pmh:oai:pure.atira.dk:openaire_cris_publications/4a8a4ba2-51cf-482c-a20f-3267eb6617d4","is_oa":false,"landing_page_url":"https://research.manchester.ac.uk/en/publications/4a8a4ba2-51cf-482c-a20f-3267eb6617d4","pdf_url":null,"source":{"id":"https://openalex.org/S4306400662","display_name":"Research Explorer (The University of Manchester)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I28407311","host_organization_name":"University of Manchester","host_organization_lineage":["https://openalex.org/I28407311"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Pavlidis, V F & Friedman, E G 2006, Via placement for minimum interconnect delay in three-dimensional (3-D) circuits. in ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings., 1693651, pp. 4587-4590, ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Kos, Greece, 21/05/06.","raw_type":"contributionToPeriodical"},{"id":"pmh:oai:pure.atira.dk:publications/4a8a4ba2-51cf-482c-a20f-3267eb6617d4","is_oa":false,"landing_page_url":"http://www.scopus.com/inward/record.url?scp=34547274914&partnerID=8YFLogxK","pdf_url":null,"source":{"id":"https://openalex.org/S4306400662","display_name":"Research Explorer (The University of Manchester)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I28407311","host_organization_name":"University of Manchester","host_organization_lineage":["https://openalex.org/I28407311"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Pavlidis, V F & Friedman, E G 2006, Via placement for minimum interconnect delay in three-dimensional (3-D) circuits. in ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Proceedings., 1693651, pp. 4587-4590, ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Kos, Greece, 21/05/06.","raw_type":"contributionToPeriodical"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8999999761581421}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1512475422","https://openalex.org/W1533690373","https://openalex.org/W1541633348","https://openalex.org/W1992651809","https://openalex.org/W2005226599","https://openalex.org/W2009195513","https://openalex.org/W2103714239","https://openalex.org/W2115529607","https://openalex.org/W2125108843","https://openalex.org/W2128142034","https://openalex.org/W2142013193","https://openalex.org/W2156918125","https://openalex.org/W2168506183","https://openalex.org/W2170288260","https://openalex.org/W2171048418","https://openalex.org/W2182510773","https://openalex.org/W2536620281","https://openalex.org/W2541669576","https://openalex.org/W6630551837"],"related_works":["https://openalex.org/W2114232017","https://openalex.org/W1927636319","https://openalex.org/W3015599398","https://openalex.org/W2792778858","https://openalex.org/W2188730438","https://openalex.org/W2367816239","https://openalex.org/W2034656493","https://openalex.org/W1875529755","https://openalex.org/W1997308464","https://openalex.org/W2123314372"],"abstract_inverted_index":{"The":[0,35,66],"propagation":[1],"delay":[2,25,46,56,87],"of":[3,37,58,86],"interlayer":[4,33],"3D":[5],"interconnects":[6,14],"is":[7,26,48,69],"investigated":[8],"in":[9,84],"this":[10,39],"paper.":[11],"For":[12],"RC":[13],"connecting":[15],"two":[16],"circuits":[17],"located":[18],"on":[19],"different":[20],"physical":[21],"planes,":[22],"the":[23,31,44],"interconnect":[24],"minimized":[27],"by":[28],"optimally":[29],"placing":[30],"non-stacked":[32],"vias.":[34],"problem":[36],"determining":[38],"optimum":[40],"via":[41,78],"locations":[42],"under":[43],"Elmore":[45],"model":[47],"described":[49],"as":[50],"a":[51,73],"geometric":[52],"program.":[53],"Simulations":[54],"indicate":[55],"improvements":[57],"up":[59],"to":[60],"26%":[61],"for":[62],"relatively":[63],"short":[64],"interconnect.":[65],"proposed":[67],"approach":[68],"also":[70],"compared":[71],"with":[72],"wire":[74],"sizing":[75],"algorithm.":[76],"Timing-driven":[77],"placement":[79],"exhibits":[80],"better":[81],"results":[82],"both":[83],"terms":[85],"and":[88],"power":[89],"consumption":[90]},"counts_by_year":[{"year":2017,"cited_by_count":1},{"year":2013,"cited_by_count":2}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}
