{"id":"https://openalex.org/W1548680868","doi":"https://doi.org/10.1109/iscas.2006.1693544","title":"A Novel, Coupling Driven, Low Power Bus Coding Technique for Minimizing Capacitive Crosstalk in VLSI Interconnects","display_name":"A Novel, Coupling Driven, Low Power Bus Coding Technique for Minimizing Capacitive Crosstalk in VLSI Interconnects","publication_year":2006,"publication_date":"2006-09-22","ids":{"openalex":"https://openalex.org/W1548680868","doi":"https://doi.org/10.1109/iscas.2006.1693544","mag":"1548680868"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2006.1693544","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2006.1693544","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5040967193","display_name":"K. S. Sainarayanan","orcid":null},"institutions":[{"id":"https://openalex.org/I107613613","display_name":"Information Technology Institute","ror":"https://ror.org/04ynw2g14","country_code":"EG","type":"facility","lineage":["https://openalex.org/I107613613"]},{"id":"https://openalex.org/I65181880","display_name":"Indian Institute of Technology Hyderabad","ror":"https://ror.org/01j4v3x97","country_code":"IN","type":"education","lineage":["https://openalex.org/I65181880"]}],"countries":["EG","IN"],"is_corresponding":true,"raw_author_name":"K.S. Sainarayanan","raw_affiliation_strings":["Center for VLSI and Embedded System Technologies (C-VEST), International Institute of Information Technology (IIIT), Hyderabad, India","[Center for VLSI & Embedded Syst. Technol., Int. Inst. of Inf. Technol., Hyderabad, India]"],"affiliations":[{"raw_affiliation_string":"Center for VLSI and Embedded System Technologies (C-VEST), International Institute of Information Technology (IIIT), Hyderabad, India","institution_ids":["https://openalex.org/I65181880"]},{"raw_affiliation_string":"[Center for VLSI & Embedded Syst. Technol., Int. Inst. of Inf. Technol., Hyderabad, India]","institution_ids":["https://openalex.org/I107613613"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5042909873","display_name":"J. V. R. Ravindra","orcid":"https://orcid.org/0000-0001-7636-1791"},"institutions":[{"id":"https://openalex.org/I107613613","display_name":"Information Technology Institute","ror":"https://ror.org/04ynw2g14","country_code":"EG","type":"facility","lineage":["https://openalex.org/I107613613"]},{"id":"https://openalex.org/I65181880","display_name":"Indian Institute of Technology Hyderabad","ror":"https://ror.org/01j4v3x97","country_code":"IN","type":"education","lineage":["https://openalex.org/I65181880"]}],"countries":["EG","IN"],"is_corresponding":false,"raw_author_name":"J.V.R. Ravindra","raw_affiliation_strings":["Center for VLSI and Embedded System Technologies (C-VEST), International Institute of Information Technology (IIIT), Hyderabad, India","[Center for VLSI & Embedded Syst. Technol., Int. Inst. of Inf. Technol., Hyderabad, India]"],"affiliations":[{"raw_affiliation_string":"Center for VLSI and Embedded System Technologies (C-VEST), International Institute of Information Technology (IIIT), Hyderabad, India","institution_ids":["https://openalex.org/I65181880"]},{"raw_affiliation_string":"[Center for VLSI & Embedded Syst. Technol., Int. Inst. of Inf. Technol., Hyderabad, India]","institution_ids":["https://openalex.org/I107613613"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101945130","display_name":"M.B. Srinivas","orcid":"https://orcid.org/0000-0003-3820-0561"},"institutions":[{"id":"https://openalex.org/I65181880","display_name":"Indian Institute of Technology Hyderabad","ror":"https://ror.org/01j4v3x97","country_code":"IN","type":"education","lineage":["https://openalex.org/I65181880"]},{"id":"https://openalex.org/I107613613","display_name":"Information Technology Institute","ror":"https://ror.org/04ynw2g14","country_code":"EG","type":"facility","lineage":["https://openalex.org/I107613613"]}],"countries":["EG","IN"],"is_corresponding":false,"raw_author_name":"M.B. Srinivas","raw_affiliation_strings":["Center for VLSI and Embedded System Technologies (C-VEST), International Institute of Information Technology (IIIT), Hyderabad, India","[Center for VLSI & Embedded Syst. Technol., Int. Inst. of Inf. Technol., Hyderabad, India]"],"affiliations":[{"raw_affiliation_string":"Center for VLSI and Embedded System Technologies (C-VEST), International Institute of Information Technology (IIIT), Hyderabad, India","institution_ids":["https://openalex.org/I65181880"]},{"raw_affiliation_string":"[Center for VLSI & Embedded Syst. Technol., Int. Inst. of Inf. Technol., Hyderabad, India]","institution_ids":["https://openalex.org/I107613613"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5040967193"],"corresponding_institution_ids":["https://openalex.org/I107613613","https://openalex.org/I65181880"],"apc_list":null,"apc_paid":null,"fwci":3.0087,"has_fulltext":false,"cited_by_count":13,"citation_normalized_percentile":{"value":0.90275047,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"4155","last_page":"4158"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/capacitance","display_name":"Capacitance","score":0.8225159645080566},{"id":"https://openalex.org/keywords/capacitive-coupling","display_name":"Capacitive coupling","score":0.6484056711196899},{"id":"https://openalex.org/keywords/capacitive-sensing","display_name":"Capacitive sensing","score":0.6077893376350403},{"id":"https://openalex.org/keywords/dissipation","display_name":"Dissipation","score":0.6050050854682922},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.58163982629776},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5673048496246338},{"id":"https://openalex.org/keywords/substrate-coupling","display_name":"Substrate coupling","score":0.5628186464309692},{"id":"https://openalex.org/keywords/crosstalk","display_name":"Crosstalk","score":0.4636825919151306},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4540749788284302},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3950386941432953},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.2876628637313843},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2785171568393707},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.199042409658432},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.13756614923477173}],"concepts":[{"id":"https://openalex.org/C30066665","wikidata":"https://www.wikidata.org/wiki/Q164399","display_name":"Capacitance","level":3,"score":0.8225159645080566},{"id":"https://openalex.org/C68278764","wikidata":"https://www.wikidata.org/wiki/Q444167","display_name":"Capacitive coupling","level":3,"score":0.6484056711196899},{"id":"https://openalex.org/C206755178","wikidata":"https://www.wikidata.org/wiki/Q1131271","display_name":"Capacitive sensing","level":2,"score":0.6077893376350403},{"id":"https://openalex.org/C135402231","wikidata":"https://www.wikidata.org/wiki/Q898440","display_name":"Dissipation","level":2,"score":0.6050050854682922},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.58163982629776},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5673048496246338},{"id":"https://openalex.org/C51674796","wikidata":"https://www.wikidata.org/wiki/Q7632167","display_name":"Substrate coupling","level":4,"score":0.5628186464309692},{"id":"https://openalex.org/C169822122","wikidata":"https://www.wikidata.org/wiki/Q230187","display_name":"Crosstalk","level":2,"score":0.4636825919151306},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4540749788284302},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3950386941432953},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.2876628637313843},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2785171568393707},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.199042409658432},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.13756614923477173},{"id":"https://openalex.org/C2779227376","wikidata":"https://www.wikidata.org/wiki/Q6505497","display_name":"Layer (electronics)","level":2,"score":0.0},{"id":"https://openalex.org/C17525397","wikidata":"https://www.wikidata.org/wiki/Q176140","display_name":"Electrode","level":2,"score":0.0},{"id":"https://openalex.org/C97355855","wikidata":"https://www.wikidata.org/wiki/Q11473","display_name":"Thermodynamics","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C155310634","wikidata":"https://www.wikidata.org/wiki/Q1852785","display_name":"Trench","level":3,"score":0.0},{"id":"https://openalex.org/C159985019","wikidata":"https://www.wikidata.org/wiki/Q181790","display_name":"Composite material","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2006.1693544","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2006.1693544","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8799999952316284,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1523576321","https://openalex.org/W1556480701","https://openalex.org/W1963518082","https://openalex.org/W2039492347","https://openalex.org/W2043630110","https://openalex.org/W2117127294","https://openalex.org/W2144493049","https://openalex.org/W2162211138","https://openalex.org/W2165072326","https://openalex.org/W2171977658","https://openalex.org/W4247998816","https://openalex.org/W4251729420","https://openalex.org/W6631444209","https://openalex.org/W6685064939"],"related_works":["https://openalex.org/W2768092448","https://openalex.org/W2895758062","https://openalex.org/W2048683560","https://openalex.org/W2044770004","https://openalex.org/W1966070768","https://openalex.org/W1994341348","https://openalex.org/W2953512238","https://openalex.org/W25797278","https://openalex.org/W4387574169","https://openalex.org/W2090054445"],"abstract_inverted_index":{"In":[0,34],"current":[1],"VLSI":[2],"technology,":[3,16,38],"interconnects":[4,20],"have":[5,128],"become":[6],"the":[7,17,26,46,52,70,91,108,132],"predominant":[8],"source":[9],"of":[10,28,45,140],"power":[11,47,101,109,133],"dissipation.":[12],"Particularly":[13],"in":[14,76,99,111],"DSM":[15],"spacing":[18],"between":[19],"is":[21,49,58,114],"very":[22],"less":[23],"leading":[24],"to":[25,51,60,95],"dominance":[27],"coupling":[29,53,97],"capacitance":[30,54],"over":[31],"self":[32,61],"capacitance.":[33,62],"0.13":[35],"/spl":[36],"mu/m":[37],"it":[39],"has":[40,135],"been":[41,129,136],"found":[42],"that":[43,89,107],"75%":[44],"consumption":[48],"due":[50,59,94],"whereas":[55],"only":[56],"25%":[57],"Thus,":[63],"earlier":[64],"schemes":[65],"which":[66],"concentrated":[67],"on":[68],"minimizing":[69],"substrate":[71],"capacitances":[72],"are":[73],"not":[74],"valid":[75],"these":[77,80],"buses.":[78],"Considering":[79],"aspects,":[81],"this":[82,120],"paper":[83],"proposes":[84],"a":[85,112],"novel":[86],"encoding":[87,121,124],"technique":[88],"reduces":[90],"switching":[92],"activity":[93],"capacitive":[96],"resulting":[98],"lower":[100],"overhead.":[102],"The":[103,123],"simulation":[104],"results":[105],"show":[106],"dissipation":[110],"bus":[113],"reduced":[115],"by":[116],"about":[117],"23%":[118],"with":[119,138],"technique.":[122],"and":[125,131],"decoding":[126],"circuits":[127],"designed":[130],"consumed":[134],"compared":[137],"those":[139],"other":[141],"coding":[142],"schemes.":[143]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}