{"id":"https://openalex.org/W2149213522","doi":"https://doi.org/10.1109/iscas.2006.1693516","title":"Reconfigurable crossbar switch architecture for network processors","display_name":"Reconfigurable crossbar switch architecture for network processors","publication_year":2006,"publication_date":"2006-09-22","ids":{"openalex":"https://openalex.org/W2149213522","doi":"https://doi.org/10.1109/iscas.2006.1693516","mag":"2149213522"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2006.1693516","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2006.1693516","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5079249940","display_name":"Henrique Cota de Freitas","orcid":"https://orcid.org/0000-0001-9722-1093"},"institutions":[{"id":"https://openalex.org/I170935008","display_name":"Pontif\u00edcia Universidade Cat\u00f3lica de Minas Gerais","ror":"https://ror.org/03j1rr444","country_code":"BR","type":"education","lineage":["https://openalex.org/I170935008"]}],"countries":["BR"],"is_corresponding":true,"raw_author_name":"H.C. Freitas","raw_affiliation_strings":["Graduate Program in Electrical Engineering, Pontifical Catholic University of Minas Gerais, Belo Horizonte, Brazil"],"affiliations":[{"raw_affiliation_string":"Graduate Program in Electrical Engineering, Pontifical Catholic University of Minas Gerais, Belo Horizonte, Brazil","institution_ids":["https://openalex.org/I170935008"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5016965917","display_name":"Milene Barbosa Carvalho","orcid":"https://orcid.org/0000-0001-7776-8446"},"institutions":[{"id":"https://openalex.org/I170935008","display_name":"Pontif\u00edcia Universidade Cat\u00f3lica de Minas Gerais","ror":"https://ror.org/03j1rr444","country_code":"BR","type":"education","lineage":["https://openalex.org/I170935008"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"M.B. Carvalho","raw_affiliation_strings":["Graduate Program in Electrical Engineering, Pontifical Catholic University of Minas Gerais, Belo Horizonte, Brazil"],"affiliations":[{"raw_affiliation_string":"Graduate Program in Electrical Engineering, Pontifical Catholic University of Minas Gerais, Belo Horizonte, Brazil","institution_ids":["https://openalex.org/I170935008"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5082558322","display_name":"Alexandre Marques Amaral","orcid":null},"institutions":[{"id":"https://openalex.org/I170935008","display_name":"Pontif\u00edcia Universidade Cat\u00f3lica de Minas Gerais","ror":"https://ror.org/03j1rr444","country_code":"BR","type":"education","lineage":["https://openalex.org/I170935008"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"A.M. Amaral","raw_affiliation_strings":["Graduate Program in Electrical Engineering, Pontifical Catholic University of Minas Gerais, Belo Horizonte, Brazil"],"affiliations":[{"raw_affiliation_string":"Graduate Program in Electrical Engineering, Pontifical Catholic University of Minas Gerais, Belo Horizonte, Brazil","institution_ids":["https://openalex.org/I170935008"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109583835","display_name":"Amanda Rafaela Diniz","orcid":null},"institutions":[{"id":"https://openalex.org/I170935008","display_name":"Pontif\u00edcia Universidade Cat\u00f3lica de Minas Gerais","ror":"https://ror.org/03j1rr444","country_code":"BR","type":"education","lineage":["https://openalex.org/I170935008"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"A.R.M. Diniz","raw_affiliation_strings":["Graduate Program in Electrical Engineering, Pontifical Catholic University of Minas Gerais, Belo Horizonte, Brazil"],"affiliations":[{"raw_affiliation_string":"Graduate Program in Electrical Engineering, Pontifical Catholic University of Minas Gerais, Belo Horizonte, Brazil","institution_ids":["https://openalex.org/I170935008"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5045477765","display_name":"Carlos Augusto Paiva da Silva Martins","orcid":"https://orcid.org/0000-0002-9856-2436"},"institutions":[{"id":"https://openalex.org/I170935008","display_name":"Pontif\u00edcia Universidade Cat\u00f3lica de Minas Gerais","ror":"https://ror.org/03j1rr444","country_code":"BR","type":"education","lineage":["https://openalex.org/I170935008"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"C.A.P.S. Martins","raw_affiliation_strings":["Graduate Program in Electrical Engineering, Pontifical Catholic University of Minas Gerais, Belo Horizonte, Brazil"],"affiliations":[{"raw_affiliation_string":"Graduate Program in Electrical Engineering, Pontifical Catholic University of Minas Gerais, Belo Horizonte, Brazil","institution_ids":["https://openalex.org/I170935008"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5036347466","display_name":"L.E.S. Ramos","orcid":null},"institutions":[{"id":"https://openalex.org/I102322142","display_name":"Rutgers, The State University of New Jersey","ror":"https://ror.org/05vt9qd57","country_code":"US","type":"education","lineage":["https://openalex.org/I102322142"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"L.E.S. Ramos","raw_affiliation_strings":["Computer Science, Rutgers University, NJ, USA"],"affiliations":[{"raw_affiliation_string":"Computer Science, Rutgers University, NJ, USA","institution_ids":["https://openalex.org/I102322142"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5079249940"],"corresponding_institution_ids":["https://openalex.org/I170935008"],"apc_list":null,"apc_paid":null,"fwci":2.5574,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.89621104,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"1142","issue":null,"first_page":"4","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/crossbar-switch","display_name":"Crossbar switch","score":0.9233732223510742},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7902559041976929},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.6397369503974915},{"id":"https://openalex.org/keywords/flexibility","display_name":"Flexibility (engineering)","score":0.6224837303161621},{"id":"https://openalex.org/keywords/middleware","display_name":"Middleware (distributed applications)","score":0.5708028674125671},{"id":"https://openalex.org/keywords/architecture","display_name":"Architecture","score":0.5688787698745728},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.45921823382377625},{"id":"https://openalex.org/keywords/message-passing","display_name":"Message passing","score":0.42080992460250854},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.3726298213005066},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.37047892808914185},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3316792845726013},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.2970565855503082},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.16294845938682556},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.11789041757583618}],"concepts":[{"id":"https://openalex.org/C29984679","wikidata":"https://www.wikidata.org/wiki/Q1929149","display_name":"Crossbar switch","level":2,"score":0.9233732223510742},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7902559041976929},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.6397369503974915},{"id":"https://openalex.org/C2780598303","wikidata":"https://www.wikidata.org/wiki/Q65921492","display_name":"Flexibility (engineering)","level":2,"score":0.6224837303161621},{"id":"https://openalex.org/C169468491","wikidata":"https://www.wikidata.org/wiki/Q146923","display_name":"Middleware (distributed applications)","level":2,"score":0.5708028674125671},{"id":"https://openalex.org/C123657996","wikidata":"https://www.wikidata.org/wiki/Q12271","display_name":"Architecture","level":2,"score":0.5688787698745728},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.45921823382377625},{"id":"https://openalex.org/C854659","wikidata":"https://www.wikidata.org/wiki/Q1859284","display_name":"Message passing","level":2,"score":0.42080992460250854},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.3726298213005066},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.37047892808914185},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3316792845726013},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.2970565855503082},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.16294845938682556},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.11789041757583618},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iscas.2006.1693516","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2006.1693516","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.418.9003","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.418.9003","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://www.research.rutgers.edu/~luramos/pdf/iscas06crossbar.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.47999998927116394,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1503658799","https://openalex.org/W1517331674","https://openalex.org/W1570135813","https://openalex.org/W1859006197","https://openalex.org/W1981281753","https://openalex.org/W2082498110","https://openalex.org/W2098165574","https://openalex.org/W2105908643","https://openalex.org/W2115294662","https://openalex.org/W2155008270","https://openalex.org/W2166329291","https://openalex.org/W6674777629","https://openalex.org/W6682791604"],"related_works":["https://openalex.org/W2145932742","https://openalex.org/W1874409533","https://openalex.org/W2554791727","https://openalex.org/W1981395029","https://openalex.org/W2108083791","https://openalex.org/W4250137794","https://openalex.org/W2122949436","https://openalex.org/W78782492","https://openalex.org/W190963477","https://openalex.org/W181593118"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"the":[3,23,42],"proposal":[4],"and":[5,25,31,41],"development":[6],"of":[7,39,44],"a":[8,47],"reconfigurable":[9],"crossbar":[10],"switch":[11],"(RCS)":[12],"architecture":[13],"for":[14,27],"network":[15],"processors.":[16],"Its":[17],"main":[18],"purpose":[19],"is":[20],"to":[21],"increase":[22],"performance,":[24],"flexibility":[26],"environments":[28],"with":[29],"multiprocessors":[30],"computer":[32],"clusters.":[33],"The":[34],"results":[35],"include":[36],"VHDL":[37],"simulation":[38],"RCS":[40],"use":[43],"it":[45],"in":[46,52],"broadcast":[48],"function":[49],"implementation,":[50],"found":[51],"message":[53],"passing":[54],"support":[55],"middleware.":[56]},"counts_by_year":[{"year":2015,"cited_by_count":1}],"updated_date":"2026-04-05T17:49:38.594831","created_date":"2025-10-10T00:00:00"}