{"id":"https://openalex.org/W1516263644","doi":"https://doi.org/10.1109/iscas.2006.1693486","title":"A register controlled delay locked loop using a TDC and a new fine delay line scheme","display_name":"A register controlled delay locked loop using a TDC and a new fine delay line scheme","publication_year":2006,"publication_date":"2006-09-22","ids":{"openalex":"https://openalex.org/W1516263644","doi":"https://doi.org/10.1109/iscas.2006.1693486","mag":"1516263644"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2006.1693486","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2006.1693486","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5015362699","display_name":"Yong Shim","orcid":"https://orcid.org/0000-0002-7101-6718"},"institutions":[{"id":"https://openalex.org/I197347611","display_name":"Korea University","ror":"https://ror.org/047dqcg40","country_code":"KR","type":"education","lineage":["https://openalex.org/I197347611"]}],"countries":["KR"],"is_corresponding":true,"raw_author_name":"Yong Shim","raw_affiliation_strings":["Department of Electronics and Computer Engineering, Korea University, Seoul, South Korea"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Computer Engineering, Korea University, Seoul, South Korea","institution_ids":["https://openalex.org/I197347611"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5107279299","display_name":"Youngkwon Jo","orcid":null},"institutions":[{"id":"https://openalex.org/I197347611","display_name":"Korea University","ror":"https://ror.org/047dqcg40","country_code":"KR","type":"education","lineage":["https://openalex.org/I197347611"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Youngkwon Jo","raw_affiliation_strings":["Department of Electronics and Computer Engineering, Korea University, Seoul, South Korea"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Computer Engineering, Korea University, Seoul, South Korea","institution_ids":["https://openalex.org/I197347611"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102874242","display_name":"Soo-Hwan Kim","orcid":"https://orcid.org/0000-0002-5394-0106"},"institutions":[{"id":"https://openalex.org/I197347611","display_name":"Korea University","ror":"https://ror.org/047dqcg40","country_code":"KR","type":"education","lineage":["https://openalex.org/I197347611"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Soohwan Kim","raw_affiliation_strings":["Department of Electronics and Computer Engineering, Korea University, Seoul, South Korea"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Computer Engineering, Korea University, Seoul, South Korea","institution_ids":["https://openalex.org/I197347611"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5040631032","display_name":"Suki Kim","orcid":null},"institutions":[{"id":"https://openalex.org/I197347611","display_name":"Korea University","ror":"https://ror.org/047dqcg40","country_code":"KR","type":"education","lineage":["https://openalex.org/I197347611"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Suki Kim","raw_affiliation_strings":["Department of Electronics and Computer Engineering, Korea University, Seoul, South Korea"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Computer Engineering, Korea University, Seoul, South Korea","institution_ids":["https://openalex.org/I197347611"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5039265204","display_name":"K.O. Cho","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Kwangjun Cho","raw_affiliation_strings":["Department of Memory design 1 Team, Hynix Semiconductor, Inc., Cheonghu, South Korea"],"affiliations":[{"raw_affiliation_string":"Department of Memory design 1 Team, Hynix Semiconductor, Inc., Cheonghu, South Korea","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5015362699"],"corresponding_institution_ids":["https://openalex.org/I197347611"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.0341715,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"40","issue":null,"first_page":"4","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9973000288009644,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/delay-locked-loop","display_name":"Delay-locked loop","score":0.7818799018859863},{"id":"https://openalex.org/keywords/loop","display_name":"Loop (graph theory)","score":0.7225835919380188},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6137365102767944},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5606127977371216},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.5575806498527527},{"id":"https://openalex.org/keywords/line","display_name":"Line (geometry)","score":0.5014712810516357},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.49357450008392334},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.48656097054481506},{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.41240304708480835},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.3274107575416565},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2357519567012787},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.1793588399887085},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.09619414806365967},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.09327057003974915}],"concepts":[{"id":"https://openalex.org/C190462668","wikidata":"https://www.wikidata.org/wiki/Q492265","display_name":"Delay-locked loop","level":4,"score":0.7818799018859863},{"id":"https://openalex.org/C184670325","wikidata":"https://www.wikidata.org/wiki/Q512604","display_name":"Loop (graph theory)","level":2,"score":0.7225835919380188},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6137365102767944},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5606127977371216},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.5575806498527527},{"id":"https://openalex.org/C198352243","wikidata":"https://www.wikidata.org/wiki/Q37105","display_name":"Line (geometry)","level":2,"score":0.5014712810516357},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.49357450008392334},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.48656097054481506},{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.41240304708480835},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.3274107575416565},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2357519567012787},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.1793588399887085},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.09619414806365967},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.09327057003974915},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2006.1693486","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2006.1693486","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8299999833106995,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320337407","display_name":"Division of Human Resource Development","ror":"https://ror.org/03mamvh39"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1540664825","https://openalex.org/W1558158353","https://openalex.org/W1925667094","https://openalex.org/W1980447189","https://openalex.org/W1997826936","https://openalex.org/W2018167528","https://openalex.org/W2097988443","https://openalex.org/W2101597431","https://openalex.org/W2117599119","https://openalex.org/W2538541815","https://openalex.org/W6640183248","https://openalex.org/W6677381565"],"related_works":["https://openalex.org/W2353997301","https://openalex.org/W2354050524","https://openalex.org/W2898479400","https://openalex.org/W1502047864","https://openalex.org/W2401743820","https://openalex.org/W3177439118","https://openalex.org/W2735947162","https://openalex.org/W2083878249","https://openalex.org/W4295813049","https://openalex.org/W2976219355"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,11,16,30,34,48,77,99],"register":[4],"controlled":[5],"delay":[6,19,44,101],"lock":[7],"loop":[8,50,68],"(RCDLL)":[9],"with":[10,65,98,108,114],"time-to-digital":[12,31],"converter":[13,32,36],"(TDC)":[14],"and":[15,47],"new":[17,86],"fine":[18],"line":[20,45],"(FDL)":[21],"scheme.":[22],"The":[23,132,141],"architecture":[24],"of":[25,42,94,144],"the":[26,56,63,82,120,123,145],"proposed":[27,90,124],"DLL":[28,58,64,125],"uses":[29],"(TDC),":[33],"digital-to-time":[35],"(DTC)":[37],"scheme":[38,88],"for":[39],"short":[40],"length":[41],"coarse":[43],"(CDL),":[46],"open":[49,67],"duty":[51],"cycle":[52],"corrector":[53],"(DCC).":[54],"While":[55],"conventional":[57,83],"has":[59,70],"two":[60],"feedback":[61],"loops,":[62],"an":[66],"DCC":[69],"only":[71],"one":[72],"loop.":[73],"So,":[74],"it":[75],"occupies":[76],"small":[78],"area":[79,143],"compared":[80],"to":[81,130],"one.":[84],"Moreover,":[85],"FDL":[87],"is":[89,92,135,147],"which":[91],"capable":[93],"seamless":[95],"boundary":[96],"switching":[97],"fixed":[100],"step.":[102],"HSPICE":[103],"simulation":[104,121],"results":[105],"are":[106],"based":[107],"ANAM":[109],"0.18mum":[110],"1P6M":[111],"CMOS":[112],"process":[113],"1.5V":[115],"power":[116,133],"supply":[117],"voltage.":[118],"Upon":[119],"results,":[122],"operates":[126],"correctly":[127],"from":[128],"200MHz":[129],"800MHz.":[131,140],"consumption":[134],"less":[136],"than":[137],"24mW":[138],"at":[139],"active":[142],"design":[146],"0.178mm":[148],"<sub":[149],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[150],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sub>":[151]},"counts_by_year":[{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}