{"id":"https://openalex.org/W1896669116","doi":"https://doi.org/10.1109/iscas.2006.1693420","title":"Low Power Low Leakage Clock Gated Static Pulsed Flip-Flop","display_name":"Low Power Low Leakage Clock Gated Static Pulsed Flip-Flop","publication_year":2006,"publication_date":"2006-09-22","ids":{"openalex":"https://openalex.org/W1896669116","doi":"https://doi.org/10.1109/iscas.2006.1693420","mag":"1896669116"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2006.1693420","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2006.1693420","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5044470095","display_name":"A. Seyedi","orcid":null},"institutions":[{"id":"https://openalex.org/I23946033","display_name":"University of Tehran","ror":"https://ror.org/05vf56z40","country_code":"IR","type":"education","lineage":["https://openalex.org/I23946033"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"A.S. Seyedi","raw_affiliation_strings":["Nanoelectronics Center of Excellence, School of Electrical and Computer Engineering, University of Tehran, Iran","Sch. of Electr. & Comput. Eng., Tehran Univ., , Iran"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Nanoelectronics Center of Excellence, School of Electrical and Computer Engineering, University of Tehran, Iran","institution_ids":["https://openalex.org/I23946033"]},{"raw_affiliation_string":"Sch. of Electr. & Comput. Eng., Tehran Univ., , Iran","institution_ids":["https://openalex.org/I23946033"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5047719857","display_name":"Seid Hadi Rasouli","orcid":"https://orcid.org/0009-0005-6159-9496"},"institutions":[{"id":"https://openalex.org/I23946033","display_name":"University of Tehran","ror":"https://ror.org/05vf56z40","country_code":"IR","type":"education","lineage":["https://openalex.org/I23946033"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"S.H. Rasouli","raw_affiliation_strings":["Nanoelectronics Center of Excellence, School of Electrical and Computer Engineering, University of Tehran, Iran","Sch. of Electr. & Comput. Eng., Tehran Univ., , Iran"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Nanoelectronics Center of Excellence, School of Electrical and Computer Engineering, University of Tehran, Iran","institution_ids":["https://openalex.org/I23946033"]},{"raw_affiliation_string":"Sch. of Electr. & Comput. Eng., Tehran Univ., , Iran","institution_ids":["https://openalex.org/I23946033"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5064574960","display_name":"Amir Amirabadi","orcid":"https://orcid.org/0000-0003-1271-7175"},"institutions":[{"id":"https://openalex.org/I23946033","display_name":"University of Tehran","ror":"https://ror.org/05vf56z40","country_code":"IR","type":"education","lineage":["https://openalex.org/I23946033"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"A. Amirabadi","raw_affiliation_strings":["Nanoelectronics Center of Excellence, School of Electrical and Computer Engineering, University of Tehran, Iran","Sch. of Electr. & Comput. Eng., Tehran Univ., , Iran"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Nanoelectronics Center of Excellence, School of Electrical and Computer Engineering, University of Tehran, Iran","institution_ids":["https://openalex.org/I23946033"]},{"raw_affiliation_string":"Sch. of Electr. & Comput. Eng., Tehran Univ., , Iran","institution_ids":["https://openalex.org/I23946033"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5074063358","display_name":"Ali Afzali\u2010Kusha","orcid":"https://orcid.org/0000-0001-8614-2007"},"institutions":[{"id":"https://openalex.org/I23946033","display_name":"University of Tehran","ror":"https://ror.org/05vf56z40","country_code":"IR","type":"education","lineage":["https://openalex.org/I23946033"]}],"countries":["IR"],"is_corresponding":false,"raw_author_name":"A. Afzali-Kusha","raw_affiliation_strings":["Nanoelectronics Center of Excellence, School of Electrical and Computer Engineering, University of Tehran, Iran","Sch. of Electr. & Comput. Eng., Tehran Univ., , Iran"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Nanoelectronics Center of Excellence, School of Electrical and Computer Engineering, University of Tehran, Iran","institution_ids":["https://openalex.org/I23946033"]},{"raw_affiliation_string":"Sch. of Electr. & Comput. Eng., Tehran Univ., , Iran","institution_ids":["https://openalex.org/I23946033"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I23946033"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"3658","last_page":"3661"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/flip-flop","display_name":"Flip-flop","score":0.8927332162857056},{"id":"https://openalex.org/keywords/leakage","display_name":"Leakage (economics)","score":0.591907262802124},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.5914854407310486},{"id":"https://openalex.org/keywords/leakage-power","display_name":"Leakage power","score":0.5677173137664795},{"id":"https://openalex.org/keywords/flops","display_name":"FLOPS","score":0.5125222206115723},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.4767342805862427},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.469867080450058},{"id":"https://openalex.org/keywords/pulse-generator","display_name":"Pulse generator","score":0.4253644347190857},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4226877689361572},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3887367844581604},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.3854903280735016},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.255909264087677},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.2406754195690155},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.2388111650943756},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.22432613372802734},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.1483021378517151},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.10606187582015991}],"concepts":[{"id":"https://openalex.org/C2781007278","wikidata":"https://www.wikidata.org/wiki/Q183406","display_name":"Flip-flop","level":3,"score":0.8927332162857056},{"id":"https://openalex.org/C2777042071","wikidata":"https://www.wikidata.org/wiki/Q6509304","display_name":"Leakage (economics)","level":2,"score":0.591907262802124},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.5914854407310486},{"id":"https://openalex.org/C2987719587","wikidata":"https://www.wikidata.org/wiki/Q1811428","display_name":"Leakage power","level":4,"score":0.5677173137664795},{"id":"https://openalex.org/C3826847","wikidata":"https://www.wikidata.org/wiki/Q188768","display_name":"FLOPS","level":2,"score":0.5125222206115723},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.4767342805862427},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.469867080450058},{"id":"https://openalex.org/C51319974","wikidata":"https://www.wikidata.org/wiki/Q3509564","display_name":"Pulse generator","level":3,"score":0.4253644347190857},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4226877689361572},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3887367844581604},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.3854903280735016},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.255909264087677},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.2406754195690155},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.2388111650943756},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.22432613372802734},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.1483021378517151},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.10606187582015991},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2006.1693420","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2006.1693420","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.9100000262260437,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1495418540","https://openalex.org/W1658200930","https://openalex.org/W1899064893","https://openalex.org/W1986692689","https://openalex.org/W2108523123","https://openalex.org/W2131862714","https://openalex.org/W2153903506","https://openalex.org/W4253764540","https://openalex.org/W6682916742"],"related_works":["https://openalex.org/W2262031297","https://openalex.org/W2080075495","https://openalex.org/W2024069812","https://openalex.org/W2056378213","https://openalex.org/W2045056374","https://openalex.org/W4386968318","https://openalex.org/W2610873304","https://openalex.org/W2039755656","https://openalex.org/W2298981088","https://openalex.org/W3202265160"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"a":[3,61],"low":[4,6,48],"power":[5,20,50,67],"leakage":[7,49],"flip-flop":[8,14,43,87],"called":[9],"clock":[10,33,56],"gated":[11],"static":[12],"pulsed":[13],"(CGSPFF)":[15],"is":[16,24,88],"proposed.":[17],"The":[18,75],"dynamic":[19],"consumption":[21,68],"in":[22,37],"CGSPFF":[23],"reduced":[25,89],"by":[26,90],"avoiding":[27],"unnecessary":[28],"input":[29],"pulse":[30,57],"transitions":[31],"with":[32],"gating.":[34],"Two":[35],"transistors":[36],"the":[38,42,54,71,78,82,85],"main":[39],"block":[40],"of":[41,77,84],"are":[44],"eliminated":[45],"to":[46,60,70],"achieve":[47],"as":[51],"well.":[52],"Using":[53],"new":[55],"generator":[58],"leads":[59],"higher":[62],"operational":[63],"speed":[64],"and":[65],"lower":[66],"compared":[69],"previously":[72],"proposed":[73,86],"flip-flops.":[74],"results":[76],"simulation":[79],"show":[80],"that":[81],"PDP":[83],"at":[91],"least":[92],"58.3%":[93]},"counts_by_year":[{"year":2016,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}