{"id":"https://openalex.org/W1815002562","doi":"https://doi.org/10.1109/iscas.2006.1693311","title":"A modeling platform for efficient characterization of phase-locked loop \u0394-\u03a3 frequency synthesizers","display_name":"A modeling platform for efficient characterization of phase-locked loop \u0394-\u03a3 frequency synthesizers","publication_year":2006,"publication_date":"2006-09-22","ids":{"openalex":"https://openalex.org/W1815002562","doi":"https://doi.org/10.1109/iscas.2006.1693311","mag":"1815002562"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2006.1693311","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2006.1693311","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5087103058","display_name":"T. Bourdi","orcid":null},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"T. Bourdi","raw_affiliation_strings":["Beceem Communications, Inc., Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Beceem Communications, Inc., Santa Clara, CA, USA","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5020620389","display_name":"A. Borjak","orcid":null},"institutions":[{"id":"https://openalex.org/I94951947","display_name":"University of Westminster","ror":"https://ror.org/04ycpbx82","country_code":"GB","type":"education","lineage":["https://openalex.org/I94951947"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"A. Borjak","raw_affiliation_strings":["Applied DSP & VLSI Research Group, Department of Electronic Systems, University of Westminster, London, UK"],"affiliations":[{"raw_affiliation_string":"Applied DSP & VLSI Research Group, Department of Electronic Systems, University of Westminster, London, UK","institution_ids":["https://openalex.org/I94951947"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5063620004","display_name":"\u0130zzet Kale","orcid":"https://orcid.org/0000-0001-5562-6885"},"institutions":[{"id":"https://openalex.org/I36515993","display_name":"Eastern Mediterranean University","ror":"https://ror.org/00excyz84","country_code":"CY","type":"education","lineage":["https://openalex.org/I36515993"]},{"id":"https://openalex.org/I94951947","display_name":"University of Westminster","ror":"https://ror.org/04ycpbx82","country_code":"GB","type":"education","lineage":["https://openalex.org/I94951947"]}],"countries":["CY","GB"],"is_corresponding":false,"raw_author_name":"I. Kale","raw_affiliation_strings":["Applied DSP & VLSI Research Group, Department of Electronic Systems, University of Westminster, London, UK","Applied DSP and VLSI Research Centre, Eastern Mediterranean University, Gazi Magusa, Mersin, Turkey"],"affiliations":[{"raw_affiliation_string":"Applied DSP & VLSI Research Group, Department of Electronic Systems, University of Westminster, London, UK","institution_ids":["https://openalex.org/I94951947"]},{"raw_affiliation_string":"Applied DSP and VLSI Research Centre, Eastern Mediterranean University, Gazi Magusa, Mersin, Turkey","institution_ids":["https://openalex.org/I36515993"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5087103058"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.05589105,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"4","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11444","display_name":"Electromagnetic Compatibility and Noise Suppression","score":0.9962000250816345,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.8047847747802734},{"id":"https://openalex.org/keywords/dither","display_name":"Dither","score":0.7533422708511353},{"id":"https://openalex.org/keywords/frequency-synthesizer","display_name":"Frequency synthesizer","score":0.7277256846427917},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.7142425775527954},{"id":"https://openalex.org/keywords/frequency-divider","display_name":"Frequency divider","score":0.6844189167022705},{"id":"https://openalex.org/keywords/direct-digital-synthesizer","display_name":"Direct digital synthesizer","score":0.6538991332054138},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5857073068618774},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5607758164405823},{"id":"https://openalex.org/keywords/noise","display_name":"Noise (video)","score":0.492872953414917},{"id":"https://openalex.org/keywords/loop","display_name":"Loop (graph theory)","score":0.4236997365951538},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3245267868041992},{"id":"https://openalex.org/keywords/noise-shaping","display_name":"Noise shaping","score":0.23279047012329102},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.11709043383598328}],"concepts":[{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.8047847747802734},{"id":"https://openalex.org/C70451592","wikidata":"https://www.wikidata.org/wiki/Q376493","display_name":"Dither","level":3,"score":0.7533422708511353},{"id":"https://openalex.org/C182099602","wikidata":"https://www.wikidata.org/wiki/Q2660678","display_name":"Frequency synthesizer","level":4,"score":0.7277256846427917},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.7142425775527954},{"id":"https://openalex.org/C74982907","wikidata":"https://www.wikidata.org/wiki/Q1455624","display_name":"Frequency divider","level":3,"score":0.6844189167022705},{"id":"https://openalex.org/C166089067","wikidata":"https://www.wikidata.org/wiki/Q1227465","display_name":"Direct digital synthesizer","level":5,"score":0.6538991332054138},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5857073068618774},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5607758164405823},{"id":"https://openalex.org/C99498987","wikidata":"https://www.wikidata.org/wiki/Q2210247","display_name":"Noise (video)","level":3,"score":0.492872953414917},{"id":"https://openalex.org/C184670325","wikidata":"https://www.wikidata.org/wiki/Q512604","display_name":"Loop (graph theory)","level":2,"score":0.4236997365951538},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3245267868041992},{"id":"https://openalex.org/C9083635","wikidata":"https://www.wikidata.org/wiki/Q2133535","display_name":"Noise shaping","level":2,"score":0.23279047012329102},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.11709043383598328},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/iscas.2006.1693311","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2006.1693311","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},{"id":"pmh:oai:westminsterresearch.westminster.ac.uk:92428","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ISCAS.2006.1693311","pdf_url":null,"source":{"id":"https://openalex.org/S4306400277","display_name":"WestminsterResearch (University of Westminster)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I94951947","host_organization_name":"University of Westminster","host_organization_lineage":["https://openalex.org/I94951947"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"acceptedVersion","is_accepted":true,"is_published":false,"raw_source_name":"","raw_type":"book-chapter"},{"id":"pmh:oai:westminsterresearch.wmin.ac.uk:3236","is_oa":false,"landing_page_url":null,"pdf_url":null,"source":{"id":"https://openalex.org/S4306400277","display_name":"WestminsterResearch (University of Westminster)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I94951947","host_organization_name":"University of Westminster","host_organization_lineage":["https://openalex.org/I94951947"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"acceptedVersion","is_accepted":true,"is_published":false,"raw_source_name":"","raw_type":"Book Section"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":1,"referenced_works":["https://openalex.org/W1840767788"],"related_works":["https://openalex.org/W3145870900","https://openalex.org/W2350523680","https://openalex.org/W2353586717","https://openalex.org/W2371350995","https://openalex.org/W2379961307","https://openalex.org/W2376421545","https://openalex.org/W2110035284","https://openalex.org/W2374761771","https://openalex.org/W2354027044","https://openalex.org/W2359366503"],"abstract_inverted_index":{"To":[0],"dramatically":[1],"reduce":[2],"the":[3,56,84,90],"need":[4],"for":[5,35,61],"silicon":[6],"reproduction":[7],"due":[8],"to":[9,45],"poor":[10],"noise":[11,78,87],"performance,":[12],"a":[13,62],"close-loop":[14],"simulation":[15,22],"platform":[16,32,58],"that":[17],"combines":[18],"both":[19],"measured":[20],"and/or":[21],"results":[23],"of":[24,72,89],"open-loop":[25],"PLL":[26],"sub-blocks":[27],"has":[28],"been":[29],"developed.":[30],"The":[31,70],"is":[33],"suited":[34],"Delta-Sigma":[36],"based":[37],"fractional-N":[38,63],"frequency":[39,64,92],"synthesizers":[40],"enabling":[41],"integrated":[42],"circuit":[43],"designers":[44],"directly":[46],"meet":[47],"cost,":[48],"performance":[49,88],"and":[50,80],"schedule":[51],"milestones.":[52],"Case":[53],"studies":[54],"employing":[55],"developed":[57],"are":[59,94],"provided":[60],"synthesizer":[65,93],"operating":[66],"near":[67],"5":[68],"GHz.":[69],"effects":[71],"dead-zone,":[73],"dithering,":[74],"near-integer":[75],"divisor":[76],"operation,":[77],"folding":[79],"prescaler":[81],"usage":[82],"on":[83],"overall":[85],"phase":[86],"entire":[91],"detailed":[95]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2016-06-24T00:00:00"}