{"id":"https://openalex.org/W1596761774","doi":"https://doi.org/10.1109/iscas.2006.1693310","title":"Phase locked loop robustness improvement using non integer order loop filter","display_name":"Phase locked loop robustness improvement using non integer order loop filter","publication_year":2006,"publication_date":"2006-09-22","ids":{"openalex":"https://openalex.org/W1596761774","doi":"https://doi.org/10.1109/iscas.2006.1693310","mag":"1596761774"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2006.1693310","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2006.1693310","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5000535820","display_name":"Vincent Lagareste","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"V. Lagareste","raw_affiliation_strings":["Microelectronics, Crolles, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microelectronics, Crolles, France","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031744532","display_name":"Franck Badets","orcid":"https://orcid.org/0000-0002-8331-4042"},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"F. Badets","raw_affiliation_strings":["Microelectronics, Crolles, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microelectronics, Crolles, France","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5084928868","display_name":"Pierre Melchior","orcid":"https://orcid.org/0000-0003-2157-8584"},"institutions":[{"id":"https://openalex.org/I15057530","display_name":"Universit\u00e9 de Bordeaux","ror":"https://ror.org/057qpr032","country_code":"FR","type":"education","lineage":["https://openalex.org/I15057530"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"P. Melchior","raw_affiliation_strings":["LAPS laboratory, CRONE Team, University of Bordeaux 1, Bordeaux, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"LAPS laboratory, CRONE Team, University of Bordeaux 1, Bordeaux, France","institution_ids":["https://openalex.org/I15057530"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5057940221","display_name":"J.B. B\u00e9gueret","orcid":"https://orcid.org/0000-0003-3245-4640"},"institutions":[{"id":"https://openalex.org/I15057530","display_name":"Universit\u00e9 de Bordeaux","ror":"https://ror.org/057qpr032","country_code":"FR","type":"education","lineage":["https://openalex.org/I15057530"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"J.B. Begueret","raw_affiliation_strings":["IXL laboratory, RF design Team, University of Bordeaux 1, Bordeaux, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IXL laboratory, RF design Team, University of Bordeaux 1, Bordeaux, France","institution_ids":["https://openalex.org/I15057530"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5068662659","display_name":"Yann Deval","orcid":"https://orcid.org/0000-0002-7358-8904"},"institutions":[{"id":"https://openalex.org/I15057530","display_name":"Universit\u00e9 de Bordeaux","ror":"https://ror.org/057qpr032","country_code":"FR","type":"education","lineage":["https://openalex.org/I15057530"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Y. Deval","raw_affiliation_strings":["IXL laboratory, RF design Team, University of Bordeaux 1, Bordeaux, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IXL laboratory, RF design Team, University of Bordeaux 1, Bordeaux, France","institution_ids":["https://openalex.org/I15057530"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5106421182","display_name":"A. Oustaloup","orcid":null},"institutions":[{"id":"https://openalex.org/I15057530","display_name":"Universit\u00e9 de Bordeaux","ror":"https://ror.org/057qpr032","country_code":"FR","type":"education","lineage":["https://openalex.org/I15057530"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"A. Oustaloup","raw_affiliation_strings":["LAPS laboratory, CRONE Team, University of Bordeaux 1, Bordeaux, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"LAPS laboratory, CRONE Team, University of Bordeaux 1, Bordeaux, France","institution_ids":["https://openalex.org/I15057530"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5108092427","display_name":"Didier Belot","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"D. Belot","raw_affiliation_strings":["Microelectronics, Crolles, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Microelectronics, Crolles, France","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"4","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.982699990272522,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12300","display_name":"Advanced Electrical Measurement Techniques","score":0.9805999994277954,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.8783127069473267},{"id":"https://openalex.org/keywords/robustness","display_name":"Robustness (evolution)","score":0.7717100977897644},{"id":"https://openalex.org/keywords/control-theory","display_name":"Control theory (sociology)","score":0.658867359161377},{"id":"https://openalex.org/keywords/delay-locked-loop","display_name":"Delay-locked loop","score":0.6057304739952087},{"id":"https://openalex.org/keywords/loop","display_name":"Loop (graph theory)","score":0.5329590439796448},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5192651748657227},{"id":"https://openalex.org/keywords/pll-multibit","display_name":"PLL multibit","score":0.4679253101348877},{"id":"https://openalex.org/keywords/frequency-synthesizer","display_name":"Frequency synthesizer","score":0.44488412141799927},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.38150981068611145},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.3140068054199219},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.23238396644592285},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19395580887794495}],"concepts":[{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.8783127069473267},{"id":"https://openalex.org/C63479239","wikidata":"https://www.wikidata.org/wiki/Q7353546","display_name":"Robustness (evolution)","level":3,"score":0.7717100977897644},{"id":"https://openalex.org/C47446073","wikidata":"https://www.wikidata.org/wiki/Q5165890","display_name":"Control theory (sociology)","level":3,"score":0.658867359161377},{"id":"https://openalex.org/C190462668","wikidata":"https://www.wikidata.org/wiki/Q492265","display_name":"Delay-locked loop","level":4,"score":0.6057304739952087},{"id":"https://openalex.org/C184670325","wikidata":"https://www.wikidata.org/wiki/Q512604","display_name":"Loop (graph theory)","level":2,"score":0.5329590439796448},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5192651748657227},{"id":"https://openalex.org/C77881186","wikidata":"https://www.wikidata.org/wiki/Q7119642","display_name":"PLL multibit","level":4,"score":0.4679253101348877},{"id":"https://openalex.org/C182099602","wikidata":"https://www.wikidata.org/wiki/Q2660678","display_name":"Frequency synthesizer","level":4,"score":0.44488412141799927},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.38150981068611145},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.3140068054199219},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.23238396644592285},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19395580887794495},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C2775924081","wikidata":"https://www.wikidata.org/wiki/Q55608371","display_name":"Control (management)","level":2,"score":0.0},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C104317684","wikidata":"https://www.wikidata.org/wiki/Q7187","display_name":"Gene","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2006.1693310","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2006.1693310","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5299999713897705,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":2,"referenced_works":["https://openalex.org/W2070541368","https://openalex.org/W2161411167"],"related_works":["https://openalex.org/W2359366503","https://openalex.org/W2474043983","https://openalex.org/W2375072050","https://openalex.org/W2330020385","https://openalex.org/W2566880546","https://openalex.org/W2376731877","https://openalex.org/W3145870900","https://openalex.org/W2371350995","https://openalex.org/W2007789933","https://openalex.org/W2544336511"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"how":[3],"noninteger":[4],"order":[5,19],"filters":[6],"can":[7],"be":[8],"used":[9],"in":[10,18,31],"phase":[11],"locked":[12],"loop":[13,36],"(PLL)":[14],"based":[15],"frequency":[16,37],"synthesizers":[17],"to":[20,26],"increase":[21],"their":[22],"stability":[23],"robustness.":[24],"Application":[25],"a":[27,32],"192MHz":[28],"PLL":[29],"involved":[30],"3.6GHz":[33],"multimode":[34],"double":[35],"synthesizer":[38],"is":[39],"described":[40]},"counts_by_year":[],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}