{"id":"https://openalex.org/W2123228218","doi":"https://doi.org/10.1109/iscas.2006.1693264","title":"Power-oriented delay budgeting for combinational circuits","display_name":"Power-oriented delay budgeting for combinational circuits","publication_year":2006,"publication_date":"2006-09-22","ids":{"openalex":"https://openalex.org/W2123228218","doi":"https://doi.org/10.1109/iscas.2006.1693264","mag":"2123228218"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2006.1693264","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2006.1693264","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5024693391","display_name":"Jialin Mi","orcid":null},"institutions":[{"id":"https://openalex.org/I74413500","display_name":"University of Windsor","ror":"https://ror.org/01gw3d370","country_code":"CA","type":"education","lineage":["https://openalex.org/I74413500"]}],"countries":["CA"],"is_corresponding":true,"raw_author_name":"Jialin Mi","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Windsor, Windsor, ONT, Canada","Dept. of Electr. & Comput. Eng, Windsor Univ., Ont., Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Windsor, Windsor, ONT, Canada","institution_ids":["https://openalex.org/I74413500"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng, Windsor Univ., Ont., Canada","institution_ids":["https://openalex.org/I74413500"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101827208","display_name":"Chunhong Chen","orcid":"https://orcid.org/0000-0001-6029-3579"},"institutions":[{"id":"https://openalex.org/I74413500","display_name":"University of Windsor","ror":"https://ror.org/01gw3d370","country_code":"CA","type":"education","lineage":["https://openalex.org/I74413500"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"Chunhong Chen","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Windsor, Windsor, ONT, Canada","Dept. of Electr. & Comput. Eng, Windsor Univ., Ont., Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Windsor, Windsor, ONT, Canada","institution_ids":["https://openalex.org/I74413500"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng, Windsor Univ., Ont., Canada","institution_ids":["https://openalex.org/I74413500"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5082995815","display_name":"Hon Keung Kwan","orcid":"https://orcid.org/0000-0003-0173-1625"},"institutions":[{"id":"https://openalex.org/I74413500","display_name":"University of Windsor","ror":"https://ror.org/01gw3d370","country_code":"CA","type":"education","lineage":["https://openalex.org/I74413500"]}],"countries":["CA"],"is_corresponding":false,"raw_author_name":"H.K. Kwan","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Windsor, Windsor, ONT, Canada","Dept. of Electr. & Comput. Eng, Windsor Univ., Ont., Canada"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Windsor, Windsor, ONT, Canada","institution_ids":["https://openalex.org/I74413500"]},{"raw_affiliation_string":"Dept. of Electr. & Comput. Eng, Windsor Univ., Ont., Canada","institution_ids":["https://openalex.org/I74413500"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5024693391"],"corresponding_institution_ids":["https://openalex.org/I74413500"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.16244418,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"4","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.7650034427642822},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.630036473274231},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6261060833930969},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.5872960090637207},{"id":"https://openalex.org/keywords/power-optimization","display_name":"Power optimization","score":0.4846530556678772},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.4609528183937073},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.4524473249912262},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3957650363445282},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3609234094619751},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.2572751045227051},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.18642058968544006},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.18343043327331543},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1344464123249054},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.12542718648910522}],"concepts":[{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.7650034427642822},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.630036473274231},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6261060833930969},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.5872960090637207},{"id":"https://openalex.org/C168292644","wikidata":"https://www.wikidata.org/wiki/Q10860336","display_name":"Power optimization","level":4,"score":0.4846530556678772},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.4609528183937073},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.4524473249912262},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3957650363445282},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3609234094619751},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.2572751045227051},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.18642058968544006},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18343043327331543},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1344464123249054},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.12542718648910522},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2006.1693264","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2006.1693264","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1511688816","https://openalex.org/W2097163769","https://openalex.org/W2101848280","https://openalex.org/W2102689227","https://openalex.org/W2132290390","https://openalex.org/W2149663872","https://openalex.org/W2155218600","https://openalex.org/W2166378964","https://openalex.org/W4242174068","https://openalex.org/W4252167597","https://openalex.org/W4256681489","https://openalex.org/W6630623413","https://openalex.org/W6675494432"],"related_works":["https://openalex.org/W29481652","https://openalex.org/W4248668797","https://openalex.org/W2110968362","https://openalex.org/W4238178324","https://openalex.org/W3141297747","https://openalex.org/W2106889348","https://openalex.org/W2111485030","https://openalex.org/W4390345338","https://openalex.org/W96064250","https://openalex.org/W2884916459"],"abstract_inverted_index":{"In":[0],"this":[1],"paper":[2],"we":[3],"propose":[4],"an":[5],"approach":[6],"of":[7,63],"providing":[8],"the":[9,28,37,50],"best":[10],"power-delay":[11],"tradeoff":[12],"for":[13],"combinational":[14],"circuits.":[15],"This":[16],"is":[17,25],"done":[18],"by":[19],"so-called":[20],"power-oriented":[21],"delay":[22,72],"budgeting":[23],"which":[24],"to":[26,59],"combine":[27],"delay-budgeting":[29],"technique":[30],"with":[31],"aggressive":[32],"power":[33,52,65],"optimization.":[34],"We":[35],"discuss":[36],"impacts":[38],"that":[39,57],"both":[40],"discrete":[41],"cell":[42],"library":[43],"and":[44],"circuit":[45],"topology":[46],"may":[47],"have":[48],"on":[49],"potential":[51],"reduction.":[53],"Experimental":[54],"results":[55],"show":[56],"up":[58],"65%":[60],"(an":[61],"average":[62],"35%)":[64],"savings":[66],"can":[67],"be":[68],"achieved":[69],"without":[70],"any":[71],"penalty.":[73]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
