{"id":"https://openalex.org/W1947007103","doi":"https://doi.org/10.1109/iscas.2006.1692996","title":"Bio-Inspired Massively Parallel Architectures for Nanotechnologies","display_name":"Bio-Inspired Massively Parallel Architectures for Nanotechnologies","publication_year":2006,"publication_date":"2006-09-22","ids":{"openalex":"https://openalex.org/W1947007103","doi":"https://doi.org/10.1109/iscas.2006.1692996","mag":"1947007103"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2006.1692996","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2006.1692996","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5070726745","display_name":"Bram de Jager","orcid":"https://orcid.org/0000-0001-5787-5981"},"institutions":[{"id":"https://openalex.org/I206945453","display_name":"Paderborn University","ror":"https://ror.org/058kzsd48","country_code":"DE","type":"education","lineage":["https://openalex.org/I206945453"]}],"countries":["DE"],"is_corresponding":true,"raw_author_name":"B. Jager","raw_affiliation_strings":["System and Circuit Technology, Heinz Nixdorf Institute, University of Paderborn, Germany","Heinz-Nixdorf Institute/Paderborn University"],"affiliations":[{"raw_affiliation_string":"System and Circuit Technology, Heinz Nixdorf Institute, University of Paderborn, Germany","institution_ids":["https://openalex.org/I206945453"]},{"raw_affiliation_string":"Heinz-Nixdorf Institute/Paderborn University","institution_ids":["https://openalex.org/I206945453"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5028498307","display_name":"Mario Porrmann","orcid":"https://orcid.org/0000-0003-1005-5753"},"institutions":[{"id":"https://openalex.org/I206945453","display_name":"Paderborn University","ror":"https://ror.org/058kzsd48","country_code":"DE","type":"education","lineage":["https://openalex.org/I206945453"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"M. Porrmann","raw_affiliation_strings":["Heinz Nixdorf Institute System and Circuit Technology, University of Paderborn, Germany","Heinz-Nixdorf Institute/Paderborn University"],"affiliations":[{"raw_affiliation_string":"Heinz Nixdorf Institute System and Circuit Technology, University of Paderborn, Germany","institution_ids":["https://openalex.org/I206945453"]},{"raw_affiliation_string":"Heinz-Nixdorf Institute/Paderborn University","institution_ids":["https://openalex.org/I206945453"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5043372144","display_name":"Ulrich R\u00fcckert","orcid":null},"institutions":[{"id":"https://openalex.org/I206945453","display_name":"Paderborn University","ror":"https://ror.org/058kzsd48","country_code":"DE","type":"education","lineage":["https://openalex.org/I206945453"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"U. Ruckert","raw_affiliation_strings":["Heinz Nixdorf Institute System and Circuit Technology, University of Paderborn, Germany","Heinz-Nixdorf Institute/Paderborn University"],"affiliations":[{"raw_affiliation_string":"Heinz Nixdorf Institute System and Circuit Technology, University of Paderborn, Germany","institution_ids":["https://openalex.org/I206945453"]},{"raw_affiliation_string":"Heinz-Nixdorf Institute/Paderborn University","institution_ids":["https://openalex.org/I206945453"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5070726745"],"corresponding_institution_ids":["https://openalex.org/I206945453"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.11030242,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1961","last_page":"1964"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9947999715805054,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/massively-parallel","display_name":"Massively parallel","score":0.8655883073806763},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8073033094406128},{"id":"https://openalex.org/keywords/energy-consumption","display_name":"Energy consumption","score":0.6165798902511597},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.5875530242919922},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5599614977836609},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.49138060212135315},{"id":"https://openalex.org/keywords/efficient-energy-use","display_name":"Efficient energy use","score":0.46732062101364136},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4204736351966858},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.36027538776397705},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.32616597414016724},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.08361515402793884},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.07817143201828003}],"concepts":[{"id":"https://openalex.org/C190475519","wikidata":"https://www.wikidata.org/wiki/Q544384","display_name":"Massively parallel","level":2,"score":0.8655883073806763},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8073033094406128},{"id":"https://openalex.org/C2780165032","wikidata":"https://www.wikidata.org/wiki/Q16869822","display_name":"Energy consumption","level":2,"score":0.6165798902511597},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.5875530242919922},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5599614977836609},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.49138060212135315},{"id":"https://openalex.org/C2742236","wikidata":"https://www.wikidata.org/wiki/Q924713","display_name":"Efficient energy use","level":2,"score":0.46732062101364136},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4204736351966858},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.36027538776397705},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.32616597414016724},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.08361515402793884},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.07817143201828003},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iscas.2006.1692996","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2006.1692996","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},{"id":"pmh:oai:pub.librecat.org:2286278","is_oa":false,"landing_page_url":"https://pub.uni-bielefeld.de/record/2286278","pdf_url":null,"source":{"id":"https://openalex.org/S4306401671","display_name":"PUB \u2013 Publications at Bielefeld University (Bielefeld University)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I20121455","host_organization_name":"Bielefeld University","host_organization_lineage":["https://openalex.org/I20121455"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"J\u00e4ger B, Porrmann M, R\u00fcckert U. Bio-inspired massively parallel architectures for nanotechnologies. In:  &lt;em&gt;Proceeding of the IEEE International Symposium on Circuits and Systems (ISCAS 2006).&lt;/em&gt; 2006: 1961-1964.","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8999999761581421,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1514972944","https://openalex.org/W1528410398","https://openalex.org/W1581868788","https://openalex.org/W2045271686","https://openalex.org/W2096856647","https://openalex.org/W2098656685","https://openalex.org/W2117085887","https://openalex.org/W2123184444","https://openalex.org/W2143331327","https://openalex.org/W2164100266","https://openalex.org/W2982757857","https://openalex.org/W3127394485","https://openalex.org/W4254440925","https://openalex.org/W6631470888"],"related_works":["https://openalex.org/W1970433854","https://openalex.org/W2023867642","https://openalex.org/W1905852083","https://openalex.org/W575709247","https://openalex.org/W113996306","https://openalex.org/W81589881","https://openalex.org/W2028391080","https://openalex.org/W2165956738","https://openalex.org/W4245589875","https://openalex.org/W2084925448"],"abstract_inverted_index":{"Massively":[0],"parallel":[1,98],"single-chip":[2],"multiprocessors":[3],"(CMP)":[4],"share":[5],"a":[6,23,49,111],"number":[7,24],"of":[8,25,33,52,58,65,83,96],"traits":[9],"with":[10,67],"biological":[11,18],"systems":[12,19],"such":[13],"as":[14,110],"neural":[15],"networks.":[16],"These":[17],"have":[20],"therefore":[21],"inspired":[22],"concepts":[26],"that":[27,36,86],"may":[28],"help":[29,88],"to":[30,69,89],"overcome":[31],"some":[32],"the":[34,63,91,107,114],"problems":[35],"will":[37,105],"come":[38],"up":[39],"in":[40,101],"future":[41],"circuit":[42],"technologies.":[43],"In":[44],"this":[45],"work":[46,103],"we":[47,104],"present":[48],"first":[50],"comparison":[51],"CMPs":[53,66],"based":[54,78],"on":[55,79],"processor":[56],"cores":[57],"different":[59,97,115],"complexity":[60],"and":[61,72,93],"estimate":[62,90],"efficiency":[64],"regards":[68],"overall":[70],"performance":[71],"energy":[73,94],"consumption.":[74],"The":[75],"analysis":[76],"is":[77],"an":[80],"analytical":[81],"model":[82],"chip":[84],"multiprocessing":[85],"can":[87],"runtime":[92],"consumption":[95],"algorithms.":[99],"As":[100],"previous":[102],"use":[106],"GigaNetIC":[108],"architecture":[109],"basis":[112],"for":[113],"CMP":[116],"architectures":[117]},"counts_by_year":[],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}
