{"id":"https://openalex.org/W1545583856","doi":"https://doi.org/10.1109/iscas.2006.1692990","title":"A mixed-structure Delay Locked-Loop with wide range and fast locking","display_name":"A mixed-structure Delay Locked-Loop with wide range and fast locking","publication_year":2006,"publication_date":"2006-09-22","ids":{"openalex":"https://openalex.org/W1545583856","doi":"https://doi.org/10.1109/iscas.2006.1692990","mag":"1545583856"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2006.1692990","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2006.1692990","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5107279299","display_name":"Youngkwon Jo","orcid":null},"institutions":[{"id":"https://openalex.org/I197347611","display_name":"Korea University","ror":"https://ror.org/047dqcg40","country_code":"KR","type":"education","lineage":["https://openalex.org/I197347611"]}],"countries":["KR"],"is_corresponding":true,"raw_author_name":"Youngkwon Jo","raw_affiliation_strings":["Department of Electronics and Computer Engineering, Korea University, Seoul, South Korea","[Dept. of Electron. & Comput. Eng., Korea Univ., Seoul, South Korea]"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Computer Engineering, Korea University, Seoul, South Korea","institution_ids":["https://openalex.org/I197347611"]},{"raw_affiliation_string":"[Dept. of Electron. & Comput. Eng., Korea Univ., Seoul, South Korea]","institution_ids":["https://openalex.org/I197347611"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5015362699","display_name":"Yong Shim","orcid":"https://orcid.org/0000-0002-7101-6718"},"institutions":[{"id":"https://openalex.org/I197347611","display_name":"Korea University","ror":"https://ror.org/047dqcg40","country_code":"KR","type":"education","lineage":["https://openalex.org/I197347611"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Yong Shim","raw_affiliation_strings":["Department of Electronics and Computer Engineering, Korea University, Seoul, South Korea","[Dept. of Electron. & Comput. Eng., Korea Univ., Seoul, South Korea]"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Computer Engineering, Korea University, Seoul, South Korea","institution_ids":["https://openalex.org/I197347611"]},{"raw_affiliation_string":"[Dept. of Electron. & Comput. Eng., Korea Univ., Seoul, South Korea]","institution_ids":["https://openalex.org/I197347611"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102874242","display_name":"Soo-Hwan Kim","orcid":"https://orcid.org/0000-0002-5394-0106"},"institutions":[{"id":"https://openalex.org/I197347611","display_name":"Korea University","ror":"https://ror.org/047dqcg40","country_code":"KR","type":"education","lineage":["https://openalex.org/I197347611"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Soohwan Kim","raw_affiliation_strings":["Department of Electronics and Computer Engineering, Korea University, Seoul, South Korea","[Dept. of Electron. & Comput. Eng., Korea Univ., Seoul, South Korea]"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Computer Engineering, Korea University, Seoul, South Korea","institution_ids":["https://openalex.org/I197347611"]},{"raw_affiliation_string":"[Dept. of Electron. & Comput. Eng., Korea Univ., Seoul, South Korea]","institution_ids":["https://openalex.org/I197347611"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5040631032","display_name":"Suki Kim","orcid":null},"institutions":[{"id":"https://openalex.org/I197347611","display_name":"Korea University","ror":"https://ror.org/047dqcg40","country_code":"KR","type":"education","lineage":["https://openalex.org/I197347611"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Suki Kim","raw_affiliation_strings":["Department of Electronics and Computer Engineering, Korea University, Seoul, South Korea","[Dept. of Electron. & Comput. Eng., Korea Univ., Seoul, South Korea]"],"affiliations":[{"raw_affiliation_string":"Department of Electronics and Computer Engineering, Korea University, Seoul, South Korea","institution_ids":["https://openalex.org/I197347611"]},{"raw_affiliation_string":"[Dept. of Electron. & Comput. Eng., Korea Univ., Seoul, South Korea]","institution_ids":["https://openalex.org/I197347611"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5043498535","display_name":"Kwanjun Cho","orcid":null},"institutions":[{"id":"https://openalex.org/I10654025","display_name":"SK Group (United States)","ror":"https://ror.org/00qajw440","country_code":"US","type":"company","lineage":["https://openalex.org/I10654025","https://openalex.org/I134353371"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kwanjun Cho","raw_affiliation_strings":["Hynix Semiconductor, Inc., Cheonghu, South Korea","[Hynix Semiconductor, Inc., Cheonghu, South Korea]"],"affiliations":[{"raw_affiliation_string":"Hynix Semiconductor, Inc., Cheonghu, South Korea","institution_ids":[]},{"raw_affiliation_string":"[Hynix Semiconductor, Inc., Cheonghu, South Korea]","institution_ids":["https://openalex.org/I10654025"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5107279299"],"corresponding_institution_ids":["https://openalex.org/I197347611"],"apc_list":null,"apc_paid":null,"fwci":0.7522,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.71412532,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"e79 c","issue":null,"first_page":"1937","last_page":"1940"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.996999979019165,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/lock","display_name":"Lock (firearm)","score":0.6841517090797424},{"id":"https://openalex.org/keywords/delay-locked-loop","display_name":"Delay-locked loop","score":0.6654638051986694},{"id":"https://openalex.org/keywords/duty-cycle","display_name":"Duty cycle","score":0.633051872253418},{"id":"https://openalex.org/keywords/loop","display_name":"Loop (graph theory)","score":0.5581748485565186},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5529325008392334},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5453673005104065},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5265969038009644},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.5185763835906982},{"id":"https://openalex.org/keywords/dissipation","display_name":"Dissipation","score":0.5130168795585632},{"id":"https://openalex.org/keywords/time-to-digital-converter","display_name":"Time-to-digital converter","score":0.5072581171989441},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.4857088029384613},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.46700629591941833},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.26436614990234375},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21034368872642517},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.15355253219604492},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.15285199880599976},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.10559871792793274}],"concepts":[{"id":"https://openalex.org/C174839445","wikidata":"https://www.wikidata.org/wiki/Q1134386","display_name":"Lock (firearm)","level":2,"score":0.6841517090797424},{"id":"https://openalex.org/C190462668","wikidata":"https://www.wikidata.org/wiki/Q492265","display_name":"Delay-locked loop","level":4,"score":0.6654638051986694},{"id":"https://openalex.org/C199822604","wikidata":"https://www.wikidata.org/wiki/Q557120","display_name":"Duty cycle","level":3,"score":0.633051872253418},{"id":"https://openalex.org/C184670325","wikidata":"https://www.wikidata.org/wiki/Q512604","display_name":"Loop (graph theory)","level":2,"score":0.5581748485565186},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5529325008392334},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5453673005104065},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5265969038009644},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.5185763835906982},{"id":"https://openalex.org/C135402231","wikidata":"https://www.wikidata.org/wiki/Q898440","display_name":"Dissipation","level":2,"score":0.5130168795585632},{"id":"https://openalex.org/C99594498","wikidata":"https://www.wikidata.org/wiki/Q2434524","display_name":"Time-to-digital converter","level":4,"score":0.5072581171989441},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.4857088029384613},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.46700629591941833},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.26436614990234375},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21034368872642517},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.15355253219604492},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.15285199880599976},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.10559871792793274},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C97355855","wikidata":"https://www.wikidata.org/wiki/Q11473","display_name":"Thermodynamics","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2006.1692990","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2006.1692990","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8299999833106995,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1515530584","https://openalex.org/W1540664825","https://openalex.org/W1558158353","https://openalex.org/W1925667094","https://openalex.org/W2039706313","https://openalex.org/W2117599119","https://openalex.org/W2175184221","https://openalex.org/W6640183248","https://openalex.org/W6660389055","https://openalex.org/W6677381565"],"related_works":["https://openalex.org/W2936029881","https://openalex.org/W2072077388","https://openalex.org/W2148370333","https://openalex.org/W2354050524","https://openalex.org/W2558486654","https://openalex.org/W2900271051","https://openalex.org/W2083878249","https://openalex.org/W2401743820","https://openalex.org/W2066428821","https://openalex.org/W3177439118"],"abstract_inverted_index":{"This":[0],"paper":[1],"describes":[2],"an":[3],"all":[4],"digital":[5,25,29],"locked-loop":[6],"(DLL)":[7],"with":[8,41,74],"a":[9,75,80,89],"mixed":[10],"structure":[11],"of":[12],"measure-controlled":[13],"DLL":[14,18,21],"(MCDLL)":[15],"and":[16,28,46,79],"register-controlled":[17],"(RCDLL).":[19],"The":[20],"utilized":[22],"time":[23,31,55],"to":[24,30,86],"converter":[26,32],"(TDC)":[27],"(DTC)":[33],"using":[34],"ring":[35],"counter":[36],"for":[37],"wide":[38,81],"range":[39,83],"operation":[40],"small":[42],"area,":[43],"fast":[44],"lock":[45,54],"duty":[47,61,66],"cycle":[48],"correction":[49,62],"(DCC).":[50],"Simulation":[51],"results":[52],"show":[53],"less":[56],"than":[57],"40":[58],"cycles,":[59],"1%":[60],"error":[63],"from":[64,84],"50plusmn10%":[65],"external":[67],"clock,":[68],"12mW":[69],"power":[70],"dissipation":[71],"at":[72],"800MHz":[73,87],"1.5V":[76],"supply":[77],"voltage":[78],"locking":[82],"100MHz":[85],"in":[88],"0.18mum":[90],"CMOS":[91],"technology":[92]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}