{"id":"https://openalex.org/W2160559566","doi":"https://doi.org/10.1109/iscas.2006.1692904","title":"Self-sampled vernier delay line for built-in clock jitter measurement","display_name":"Self-sampled vernier delay line for built-in clock jitter measurement","publication_year":2006,"publication_date":"2006-09-22","ids":{"openalex":"https://openalex.org/W2160559566","doi":"https://doi.org/10.1109/iscas.2006.1692904","mag":"2160559566"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2006.1692904","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2006.1692904","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101981427","display_name":"Kuo\u2010Hsing Cheng","orcid":"https://orcid.org/0000-0002-0997-5264"},"institutions":[{"id":"https://openalex.org/I22265921","display_name":"National Central University","ror":"https://ror.org/00944ve71","country_code":"TW","type":"education","lineage":["https://openalex.org/I22265921"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Kuo-Hsing Cheng","raw_affiliation_strings":["Department of Electrical Engineering, National Central University, Taoyuan, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Central University, Taoyuan, Taiwan","institution_ids":["https://openalex.org/I22265921"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101165191","display_name":"Chan-Wei Huang","orcid":null},"institutions":[{"id":"https://openalex.org/I22265921","display_name":"National Central University","ror":"https://ror.org/00944ve71","country_code":"TW","type":"education","lineage":["https://openalex.org/I22265921"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chan-Wei Huang","raw_affiliation_strings":["Department of Electrical Engineering, National Central University, Taoyuan, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Central University, Taoyuan, Taiwan","institution_ids":["https://openalex.org/I22265921"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5112413920","display_name":"Shuyu Jiang","orcid":null},"institutions":[{"id":"https://openalex.org/I22265921","display_name":"National Central University","ror":"https://ror.org/00944ve71","country_code":"TW","type":"education","lineage":["https://openalex.org/I22265921"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Shu-Yu Jiang","raw_affiliation_strings":["Department of Electrical Engineering, National Central University, Taoyuan, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Central University, Taoyuan, Taiwan","institution_ids":["https://openalex.org/I22265921"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5101981427"],"corresponding_institution_ids":["https://openalex.org/I22265921"],"apc_list":null,"apc_paid":null,"fwci":0.7522,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.75941667,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1591","last_page":"1594"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.927331805229187},{"id":"https://openalex.org/keywords/vernier-scale","display_name":"Vernier scale","score":0.8959715366363525},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5861687064170837},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5803362727165222},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4843207895755768},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.481931209564209},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.43945932388305664},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.41769590973854065},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.4139356315135956},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3232453167438507},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21020355820655823},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.14001694321632385},{"id":"https://openalex.org/keywords/optics","display_name":"Optics","score":0.12087056040763855},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.10447865724563599}],"concepts":[{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.927331805229187},{"id":"https://openalex.org/C69710193","wikidata":"https://www.wikidata.org/wiki/Q14946576","display_name":"Vernier scale","level":2,"score":0.8959715366363525},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5861687064170837},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5803362727165222},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4843207895755768},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.481931209564209},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.43945932388305664},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.41769590973854065},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.4139356315135956},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3232453167438507},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21020355820655823},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.14001694321632385},{"id":"https://openalex.org/C120665830","wikidata":"https://www.wikidata.org/wiki/Q14620","display_name":"Optics","level":1,"score":0.12087056040763855},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10447865724563599}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2006.1692904","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2006.1692904","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.5,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W1691451471","https://openalex.org/W1891123279","https://openalex.org/W2126936678","https://openalex.org/W2148172069"],"related_works":["https://openalex.org/W2107482880","https://openalex.org/W2119823365","https://openalex.org/W2155236300","https://openalex.org/W2370061661","https://openalex.org/W2090237663","https://openalex.org/W2116514610","https://openalex.org/W1506442459","https://openalex.org/W2052455055","https://openalex.org/W2003180247","https://openalex.org/W1574257586"],"abstract_inverted_index":{"For":[0],"high-speed":[1],"analog":[2],"and":[3,22],"mixed":[4],"signal":[5],"circuits,":[6],"on-chip":[7],"clock":[8,60],"jitter":[9,57],"measurement":[10,90],"has":[11],"been":[12],"a":[13],"challenge":[14],"in":[15,62,71,92],"recent":[16],"years.":[17],"Circuit":[18],"resolution,":[19,75],"chip":[20,80],"area,":[21],"frequency":[23],"range":[24,91],"are":[25],"critical":[26],"specification":[27],"for":[28,84],"built-in-test":[29],"(BIT)":[30],"circuit":[31,68,74],"design.":[32,64],"In":[33],"order":[34],"to":[35,87],"fulfil":[36],"these":[37],"requirements,":[38],"the":[39,66],"self-sampled":[40],"Vernier":[41],"delay":[42],"line":[43],"(VDL)":[44],"structure":[45],"is":[46,54,69,82],"proposed.":[47],"Comparing":[48],"with":[49],"traditional":[50],"VDL":[51],"structure,":[52],"there":[53],"no":[55],"more":[56],"free":[58],"sample":[59],"used":[61,83],"this":[63],"When":[65],"proposed":[67],"designed":[70],"14":[72],"ps":[73],"only":[76],"500/spl":[77],"mu/m*750/spl":[78],"mu/m":[79,95],"area":[81],"100":[85],"MHz":[86,89],"400":[88],"TSMC":[93],"0.35/spl":[94],"CMOS":[96],"process.":[97]},"counts_by_year":[{"year":2013,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
