{"id":"https://openalex.org/W2116538501","doi":"https://doi.org/10.1109/iscas.2006.1692893","title":"A new bulk-driven input stage design for sub 1-volt CMOS op-amps","display_name":"A new bulk-driven input stage design for sub 1-volt CMOS op-amps","publication_year":2006,"publication_date":"2006-09-22","ids":{"openalex":"https://openalex.org/W2116538501","doi":"https://doi.org/10.1109/iscas.2006.1692893","mag":"2116538501"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2006.1692893","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2006.1692893","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5009400823","display_name":"Yasutaka Haga","orcid":null},"institutions":[{"id":"https://openalex.org/I94951947","display_name":"University of Westminster","ror":"https://ror.org/04ycpbx82","country_code":"GB","type":"education","lineage":["https://openalex.org/I94951947"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Y. Haga","raw_affiliation_strings":["Applied DSP & VLSI Research Group, Department of Electronic Systems, University of Westminster, London, UK"],"affiliations":[{"raw_affiliation_string":"Applied DSP & VLSI Research Group, Department of Electronic Systems, University of Westminster, London, UK","institution_ids":["https://openalex.org/I94951947"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5113660449","display_name":"R.C.S. Morling","orcid":null},"institutions":[{"id":"https://openalex.org/I94951947","display_name":"University of Westminster","ror":"https://ror.org/04ycpbx82","country_code":"GB","type":"education","lineage":["https://openalex.org/I94951947"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"R.C.S. Morling","raw_affiliation_strings":["Applied DSP & VLSI Research Group, Department of Electronic Systems, University of Westminster, London, UK"],"affiliations":[{"raw_affiliation_string":"Applied DSP & VLSI Research Group, Department of Electronic Systems, University of Westminster, London, UK","institution_ids":["https://openalex.org/I94951947"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5063620004","display_name":"\u0130zzet Kale","orcid":"https://orcid.org/0000-0001-5562-6885"},"institutions":[{"id":"https://openalex.org/I94951947","display_name":"University of Westminster","ror":"https://ror.org/04ycpbx82","country_code":"GB","type":"education","lineage":["https://openalex.org/I94951947"]},{"id":"https://openalex.org/I36515993","display_name":"Eastern Mediterranean University","ror":"https://ror.org/00excyz84","country_code":"CY","type":"education","lineage":["https://openalex.org/I36515993"]}],"countries":["CY","GB"],"is_corresponding":false,"raw_author_name":"I. Kale","raw_affiliation_strings":["Applied DSP & VLSI Research Group, Department of Electronic Systems, University of Westminster, London, UK","Applied DSP and VLSI Research Centre, Eastern Mediterranean University, Gazi Magusa, Mersin, Turkey"],"affiliations":[{"raw_affiliation_string":"Applied DSP & VLSI Research Group, Department of Electronic Systems, University of Westminster, London, UK","institution_ids":["https://openalex.org/I94951947"]},{"raw_affiliation_string":"Applied DSP and VLSI Research Centre, Eastern Mediterranean University, Gazi Magusa, Mersin, Turkey","institution_ids":["https://openalex.org/I36515993"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5009400823"],"corresponding_institution_ids":["https://openalex.org/I94951947"],"apc_list":null,"apc_paid":null,"fwci":0.5764,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.7227412,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"4","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.8289159536361694},{"id":"https://openalex.org/keywords/transconductance","display_name":"Transconductance","score":0.7997016906738281},{"id":"https://openalex.org/keywords/slew-rate","display_name":"Slew rate","score":0.6802979111671448},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.547107994556427},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.4980335235595703},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.4772734045982361},{"id":"https://openalex.org/keywords/operational-amplifier","display_name":"Operational amplifier","score":0.4472726285457611},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4104601740837097},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.37780943512916565},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.31369298696517944},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.24713173508644104},{"id":"https://openalex.org/keywords/amplifier","display_name":"Amplifier","score":0.09836050868034363}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.8289159536361694},{"id":"https://openalex.org/C2779283907","wikidata":"https://www.wikidata.org/wiki/Q1632964","display_name":"Transconductance","level":4,"score":0.7997016906738281},{"id":"https://openalex.org/C82517063","wikidata":"https://www.wikidata.org/wiki/Q1591315","display_name":"Slew rate","level":3,"score":0.6802979111671448},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.547107994556427},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.4980335235595703},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.4772734045982361},{"id":"https://openalex.org/C145366948","wikidata":"https://www.wikidata.org/wiki/Q178947","display_name":"Operational amplifier","level":4,"score":0.4472726285457611},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4104601740837097},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.37780943512916565},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.31369298696517944},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.24713173508644104},{"id":"https://openalex.org/C194257627","wikidata":"https://www.wikidata.org/wiki/Q211554","display_name":"Amplifier","level":3,"score":0.09836050868034363}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/iscas.2006.1692893","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2006.1692893","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},{"id":"pmh:oai:westminsterresearch.westminster.ac.uk:92577","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ISCAS.2006.1692893","pdf_url":null,"source":{"id":"https://openalex.org/S4306400277","display_name":"WestminsterResearch (University of Westminster)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I94951947","host_organization_name":"University of Westminster","host_organization_lineage":["https://openalex.org/I94951947"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"acceptedVersion","is_accepted":true,"is_published":false,"raw_source_name":"","raw_type":"book-chapter"},{"id":"pmh:oai:westminsterresearch.wmin.ac.uk:3340","is_oa":false,"landing_page_url":null,"pdf_url":null,"source":{"id":"https://openalex.org/S4306400277","display_name":"WestminsterResearch (University of Westminster)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I94951947","host_organization_name":"University of Westminster","host_organization_lineage":["https://openalex.org/I94951947"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"acceptedVersion","is_accepted":true,"is_published":false,"raw_source_name":"","raw_type":"Book Section"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.6700000166893005,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":14,"referenced_works":["https://openalex.org/W1536945048","https://openalex.org/W1566916904","https://openalex.org/W1919185684","https://openalex.org/W1986138116","https://openalex.org/W2033021170","https://openalex.org/W2036779818","https://openalex.org/W2080615209","https://openalex.org/W2105670259","https://openalex.org/W2117471170","https://openalex.org/W2137884321","https://openalex.org/W2157637127","https://openalex.org/W2165367094","https://openalex.org/W2767979639","https://openalex.org/W6701316451"],"related_works":["https://openalex.org/W101534108","https://openalex.org/W1500249877","https://openalex.org/W2134780641","https://openalex.org/W2425085424","https://openalex.org/W2083204540","https://openalex.org/W4235119538","https://openalex.org/W1938109932","https://openalex.org/W1972136484","https://openalex.org/W1946609993","https://openalex.org/W2035092043"],"abstract_inverted_index":{"This":[0,23],"paper":[1],"presents":[2],"a":[3,8,14,43],"new":[4],"design":[5],"approach":[6],"for":[7,65],"rail-to-rail":[9],"bulk-driven":[10],"input":[11,24,38],"stage":[12,25],"using":[13],"standard":[15],"single-well":[16],"(n-well":[17],"in":[18],"this":[19],"paper)":[20],"CMOS":[21,67],"technology.":[22],"can":[26],"provide":[27],"nearly":[28],"constant":[29,32],"transconductance":[30],"and":[31],"slew":[33],"rate":[34],"over":[35],"the":[36,62,66],"entire":[37],"common-mode":[39],"voltage,":[40],"operating":[41],"with":[42],"wide":[44],"supply":[45],"voltage":[46],"ranging":[47],"from":[48],"sub":[49],"1-volt":[50],"(V":[51],"<sub":[52,57],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[53,58],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">T0</sub>":[54],"+":[55],"3V":[56],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">DSsat</sub>":[59],")":[60],"to":[61],"maximum":[63],"allowed":[64],"process,":[68],"as":[69,71],"well":[70],"preventing":[72],"latch-up":[73]},"counts_by_year":[{"year":2013,"cited_by_count":3},{"year":2012,"cited_by_count":1}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}