{"id":"https://openalex.org/W1724532631","doi":"https://doi.org/10.1109/iscas.2006.1692878","title":"Segmentation based design of serial parallel multipliers","display_name":"Segmentation based design of serial parallel multipliers","publication_year":2006,"publication_date":"2006-09-22","ids":{"openalex":"https://openalex.org/W1724532631","doi":"https://doi.org/10.1109/iscas.2006.1692878","mag":"1724532631"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2006.1692878","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2006.1692878","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://doi.org/10.1109/ISCAS.2006.1692878","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5013071475","display_name":"P. Bougas","orcid":null},"institutions":[{"id":"https://openalex.org/I174458059","display_name":"National Technical University of Athens","ror":"https://ror.org/03cx6bg69","country_code":"GR","type":"education","lineage":["https://openalex.org/I174458059"]}],"countries":["GR"],"is_corresponding":true,"raw_author_name":"P. Bougas","raw_affiliation_strings":["School of Electrical and Computer Engineering, National and Technical University of Athens, Athens, Greece","Sch. of Electr. & Comput. Eng., Athens Nat. Tech. Univ"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, National and Technical University of Athens, Athens, Greece","institution_ids":["https://openalex.org/I174458059"]},{"raw_affiliation_string":"Sch. of Electr. & Comput. Eng., Athens Nat. Tech. Univ","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005740365","display_name":"A.S. Tsirikos","orcid":null},"institutions":[{"id":"https://openalex.org/I174458059","display_name":"National Technical University of Athens","ror":"https://ror.org/03cx6bg69","country_code":"GR","type":"education","lineage":["https://openalex.org/I174458059"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"A. Tsirikos","raw_affiliation_strings":["School of Electrical and Computer Engineering, National and Technical University of Athens, Athens, Greece","Sch. of Electr. & Comput. Eng., Athens Nat. Tech. Univ"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, National and Technical University of Athens, Athens, Greece","institution_ids":["https://openalex.org/I174458059"]},{"raw_affiliation_string":"Sch. of Electr. & Comput. Eng., Athens Nat. Tech. Univ","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5026787221","display_name":"\u039a\u03c9\u03bd\u03c3\u03c4\u03b1\u03bd\u03c4\u03af\u03bd\u03bf\u03c2 \u0391\u03bd\u03b1\u03b3\u03bd\u03c9\u03c3\u03c4\u03cc\u03c0\u03bf\u03c5\u03bb\u03bf\u03c2","orcid":"https://orcid.org/0000-0001-7775-5987"},"institutions":[{"id":"https://openalex.org/I174458059","display_name":"National Technical University of Athens","ror":"https://ror.org/03cx6bg69","country_code":"GR","type":"education","lineage":["https://openalex.org/I174458059"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"K. Anagnostopoulos","raw_affiliation_strings":["School of Electrical and Computer Engineering, National and Technical University of Athens, Athens, Greece","Sch. of Electr. & Comput. Eng., Athens Nat. Tech. Univ"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, National and Technical University of Athens, Athens, Greece","institution_ids":["https://openalex.org/I174458059"]},{"raw_affiliation_string":"Sch. of Electr. & Comput. Eng., Athens Nat. Tech. Univ","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5069705909","display_name":"Isidoros Sideris","orcid":null},"institutions":[{"id":"https://openalex.org/I174458059","display_name":"National Technical University of Athens","ror":"https://ror.org/03cx6bg69","country_code":"GR","type":"education","lineage":["https://openalex.org/I174458059"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"I. Sideris","raw_affiliation_strings":["School of Electrical and Computer Engineering, National and Technical University of Athens, Athens, Greece","Sch. of Electr. & Comput. Eng., Athens Nat. Tech. Univ"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, National and Technical University of Athens, Athens, Greece","institution_ids":["https://openalex.org/I174458059"]},{"raw_affiliation_string":"Sch. of Electr. & Comput. Eng., Athens Nat. Tech. Univ","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5088085592","display_name":"Kiamal Pekmestzi","orcid":"https://orcid.org/0000-0001-8612-2700"},"institutions":[{"id":"https://openalex.org/I174458059","display_name":"National Technical University of Athens","ror":"https://ror.org/03cx6bg69","country_code":"GR","type":"education","lineage":["https://openalex.org/I174458059"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"K. Pekmestzi","raw_affiliation_strings":["School of Electrical and Computer Engineering, National and Technical University of Athens, Athens, Greece","Sch. of Electr. & Comput. Eng., Athens Nat. Tech. Univ"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, National and Technical University of Athens, Athens, Greece","institution_ids":["https://openalex.org/I174458059"]},{"raw_affiliation_string":"Sch. of Electr. & Comput. Eng., Athens Nat. Tech. Univ","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5013071475"],"corresponding_institution_ids":["https://openalex.org/I174458059"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.05894211,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":"c 23","issue":null,"first_page":"4","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.7927663326263428},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7348477840423584},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.5622586607933044},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5456522107124329},{"id":"https://openalex.org/keywords/segmentation","display_name":"Segmentation","score":0.52641361951828},{"id":"https://openalex.org/keywords/multiplication","display_name":"Multiplication (music)","score":0.4933072626590729},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4441494047641754},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.4252648949623108},{"id":"https://openalex.org/keywords/arithmetic","display_name":"Arithmetic","score":0.41541197896003723},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3842329978942871},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.16860735416412354},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.14024361968040466}],"concepts":[{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.7927663326263428},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7348477840423584},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.5622586607933044},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5456522107124329},{"id":"https://openalex.org/C89600930","wikidata":"https://www.wikidata.org/wiki/Q1423946","display_name":"Segmentation","level":2,"score":0.52641361951828},{"id":"https://openalex.org/C2780595030","wikidata":"https://www.wikidata.org/wiki/Q3860309","display_name":"Multiplication (music)","level":2,"score":0.4933072626590729},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4441494047641754},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.4252648949623108},{"id":"https://openalex.org/C94375191","wikidata":"https://www.wikidata.org/wiki/Q11205","display_name":"Arithmetic","level":1,"score":0.41541197896003723},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3842329978942871},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.16860735416412354},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.14024361968040466},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.0},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iscas.2006.1692878","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2006.1692878","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},{"id":"pmh:oai:dspace.lib.ntua.gr:123456789/31735","is_oa":true,"landing_page_url":"http://doi.org/10.1109/ISCAS.2006.1692878","pdf_url":null,"source":{"id":"https://openalex.org/S4377196837","display_name":"DSpace - NTUA (National Technical University of Athens)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I174458059","host_organization_name":"National Technical University of Athens","host_organization_lineage":["https://openalex.org/I174458059"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Proceedings - IEEE International Symposium on Circuits and Systems","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":{"id":"pmh:oai:dspace.lib.ntua.gr:123456789/31735","is_oa":true,"landing_page_url":"http://doi.org/10.1109/ISCAS.2006.1692878","pdf_url":null,"source":{"id":"https://openalex.org/S4377196837","display_name":"DSpace - NTUA (National Technical University of Athens)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I174458059","host_organization_name":"National Technical University of Athens","host_organization_lineage":["https://openalex.org/I174458059"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Proceedings - IEEE International Symposium on Circuits and Systems","raw_type":"info:eu-repo/semantics/conferenceObject"},"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","score":0.47999998927116394,"id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1969754336","https://openalex.org/W1976891713","https://openalex.org/W1987510526","https://openalex.org/W2017853123","https://openalex.org/W2018477922","https://openalex.org/W2048773562","https://openalex.org/W2049872805","https://openalex.org/W2052729261","https://openalex.org/W2054671629","https://openalex.org/W2084932969","https://openalex.org/W2090680947","https://openalex.org/W2092564026","https://openalex.org/W2128501984","https://openalex.org/W2130904320","https://openalex.org/W2139130401","https://openalex.org/W2153691819","https://openalex.org/W2159281893","https://openalex.org/W2591602111","https://openalex.org/W6683318224"],"related_works":["https://openalex.org/W2013839957","https://openalex.org/W2171373222","https://openalex.org/W3196607417","https://openalex.org/W2036954759","https://openalex.org/W2057797376","https://openalex.org/W2090319426","https://openalex.org/W2506252583","https://openalex.org/W2048249848","https://openalex.org/W4281295723","https://openalex.org/W2067758538"],"abstract_inverted_index":{"In":[0],"this":[1],"paper,":[2],"a":[3,22,26,49,54],"novel":[4],"architecture":[5],"for":[6],"the":[7,65,73,76],"implementation":[8],"of":[9,25,31,45,75],"serial":[10],"parallel":[11],"multipliers":[12],"(SPM)":[13],"is":[14,19],"proposed.":[15],"The":[16,69],"proposed":[17,70],"multiplier":[18,36],"based":[20],"on":[21],"segmentation":[23],"technique":[24,71],"simple":[27],"SPM":[28],"to":[29,47,64],"blocks":[30],"equal":[32],"bit":[33],"length.":[34],"This":[35],"achieves":[37,59],"higher":[38],"throughput":[39],"because":[40],"it":[41],"requires":[42],"small":[43],"number":[44],"zeros":[46],"start":[48],"new":[50],"multiplication":[51],"cycle":[52],"at":[53],"moderate":[55],"hardware":[56,61],"expense":[57],"and":[58],"significant":[60],"reduction":[62],"compared":[63],"double":[66],"precision":[67],"SPM.":[68],"permits":[72],"optimization":[74],"area":[77],"time":[78],"product":[79]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-03-20T23:20:44.827607","created_date":"2025-10-10T00:00:00"}