{"id":"https://openalex.org/W1785410663","doi":"https://doi.org/10.1109/iscas.2006.1692877","title":"Bit level architectural exploration technique for the design of low power multipliers","display_name":"Bit level architectural exploration technique for the design of low power multipliers","publication_year":2006,"publication_date":"2006-09-22","ids":{"openalex":"https://openalex.org/W1785410663","doi":"https://doi.org/10.1109/iscas.2006.1692877","mag":"1785410663"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2006.1692877","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2006.1692877","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://doi.org/10.1109/ISCAS.2006.1692877","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5089110665","display_name":"George Economakos","orcid":null},"institutions":[{"id":"https://openalex.org/I200777214","display_name":"National and Kapodistrian University of Athens","ror":"https://ror.org/04gnjpq42","country_code":"GR","type":"education","lineage":["https://openalex.org/I200777214"]},{"id":"https://openalex.org/I174458059","display_name":"National Technical University of Athens","ror":"https://ror.org/03cx6bg69","country_code":"GR","type":"education","lineage":["https://openalex.org/I174458059"]}],"countries":["GR"],"is_corresponding":true,"raw_author_name":"G. Economakos","raw_affiliation_strings":["School of Electrical and Computer Engineering, Microprocessors and Digital Systems Laboratory, National and Technical University of Athens, Athens, Greece","Sch. of Electr. & Comput. Eng., National Tech. Univ. of Athens#TAB#"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Microprocessors and Digital Systems Laboratory, National and Technical University of Athens, Athens, Greece","institution_ids":["https://openalex.org/I174458059"]},{"raw_affiliation_string":"Sch. of Electr. & Comput. Eng., National Tech. Univ. of Athens#TAB#","institution_ids":["https://openalex.org/I200777214"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5026787221","display_name":"\u039a\u03c9\u03bd\u03c3\u03c4\u03b1\u03bd\u03c4\u03af\u03bd\u03bf\u03c2 \u0391\u03bd\u03b1\u03b3\u03bd\u03c9\u03c3\u03c4\u03cc\u03c0\u03bf\u03c5\u03bb\u03bf\u03c2","orcid":"https://orcid.org/0000-0001-7775-5987"},"institutions":[{"id":"https://openalex.org/I174458059","display_name":"National Technical University of Athens","ror":"https://ror.org/03cx6bg69","country_code":"GR","type":"education","lineage":["https://openalex.org/I174458059"]},{"id":"https://openalex.org/I200777214","display_name":"National and Kapodistrian University of Athens","ror":"https://ror.org/04gnjpq42","country_code":"GR","type":"education","lineage":["https://openalex.org/I200777214"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"K. Anagnostopoulos","raw_affiliation_strings":["School of Electrical and Computer Engineering, Microprocessors and Digital Systems Laboratory, National and Technical University of Athens, Athens, Greece","Sch. of Electr. & Comput. Eng., National Tech. Univ. of Athens#TAB#"],"affiliations":[{"raw_affiliation_string":"School of Electrical and Computer Engineering, Microprocessors and Digital Systems Laboratory, National and Technical University of Athens, Athens, Greece","institution_ids":["https://openalex.org/I174458059"]},{"raw_affiliation_string":"Sch. of Electr. & Comput. Eng., National Tech. Univ. of Athens#TAB#","institution_ids":["https://openalex.org/I200777214"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5089110665"],"corresponding_institution_ids":["https://openalex.org/I174458059","https://openalex.org/I200777214"],"apc_list":null,"apc_paid":null,"fwci":1.9106,"has_fulltext":false,"cited_by_count":16,"citation_normalized_percentile":{"value":0.8492807,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"4","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6598819494247437},{"id":"https://openalex.org/keywords/multiplier","display_name":"Multiplier (economics)","score":0.5504162311553955},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5306046605110168},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.5167405009269714},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.5006723403930664},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.47643405199050903},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.45394212007522583},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.43859919905662537},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.42672282457351685},{"id":"https://openalex.org/keywords/tree","display_name":"Tree (set theory)","score":0.4183272123336792},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4139416515827179},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.41369158029556274},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.18805238604545593},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1829988658428192},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.16012603044509888},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.1501758098602295},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.10272955894470215}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6598819494247437},{"id":"https://openalex.org/C124584101","wikidata":"https://www.wikidata.org/wiki/Q1053266","display_name":"Multiplier (economics)","level":2,"score":0.5504162311553955},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5306046605110168},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.5167405009269714},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.5006723403930664},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.47643405199050903},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.45394212007522583},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.43859919905662537},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.42672282457351685},{"id":"https://openalex.org/C113174947","wikidata":"https://www.wikidata.org/wiki/Q2859736","display_name":"Tree (set theory)","level":2,"score":0.4183272123336792},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4139416515827179},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.41369158029556274},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.18805238604545593},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1829988658428192},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.16012603044509888},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.1501758098602295},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10272955894470215},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C82876162","wikidata":"https://www.wikidata.org/wiki/Q17096504","display_name":"Latency (audio)","level":2,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iscas.2006.1692877","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2006.1692877","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},{"id":"pmh:oai:dspace.lib.ntua.gr:123456789/31577","is_oa":true,"landing_page_url":"http://doi.org/10.1109/ISCAS.2006.1692877","pdf_url":null,"source":{"id":"https://openalex.org/S4377196837","display_name":"DSpace - NTUA (National Technical University of Athens)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I174458059","host_organization_name":"National Technical University of Athens","host_organization_lineage":["https://openalex.org/I174458059"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Proceedings - IEEE International Symposium on Circuits and Systems","raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":{"id":"pmh:oai:dspace.lib.ntua.gr:123456789/31577","is_oa":true,"landing_page_url":"http://doi.org/10.1109/ISCAS.2006.1692877","pdf_url":null,"source":{"id":"https://openalex.org/S4377196837","display_name":"DSpace - NTUA (National Technical University of Athens)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I174458059","host_organization_name":"National Technical University of Athens","host_organization_lineage":["https://openalex.org/I174458059"],"host_organization_lineage_names":[],"type":"repository"},"license":"other-oa","license_id":"https://openalex.org/licenses/other-oa","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Proceedings - IEEE International Symposium on Circuits and Systems","raw_type":"info:eu-repo/semantics/conferenceObject"},"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8700000047683716,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1496146811","https://openalex.org/W1518236483","https://openalex.org/W1539883310","https://openalex.org/W1794223190","https://openalex.org/W1983849809","https://openalex.org/W2137718401","https://openalex.org/W2149565956","https://openalex.org/W2533272068","https://openalex.org/W3145549963","https://openalex.org/W6793399246"],"related_works":["https://openalex.org/W2121819644","https://openalex.org/W4226372077","https://openalex.org/W4239625882","https://openalex.org/W2072840391","https://openalex.org/W818963952","https://openalex.org/W2157277696","https://openalex.org/W2018106661","https://openalex.org/W2039140951","https://openalex.org/W1939541994","https://openalex.org/W1851795671"],"abstract_inverted_index":{"In":[0],"this":[1,65],"paper":[2],"a":[3,81,87,110],"new":[4],"technique":[5],"for":[6,12,83],"the":[7,51,55,72,76,84,100],"design":[8],"of":[9,24,44,54,75],"combinational":[10],"circuits":[11],"low":[13,33,61],"power":[14,62,105],"is":[15,20,29,47,57,67,80,96],"introduced.":[16],"The":[17,41],"basic":[18],"idea":[19],"to":[21,60,69],"bypass":[22,94],"blocks":[23,46],"logic":[25],"when":[26],"their":[27],"function":[28],"not":[30],"required,":[31],"using":[32,90],"delay":[34],"and":[35,93,107],"area":[36,74,113],"overhead":[37],"components":[38],"(transmission":[39],"gates).":[40],"internal":[42],"state":[43],"these":[45],"kept":[48],"unchanged,":[49],"so":[50],"switching":[52],"activity":[53],"circuit":[56],"minimized,":[58],"resulting":[59],"consumption.":[63],"While":[64],"ideas":[66],"applicable":[68],"array":[70],"multipliers,":[71],"reduced":[73],"Wallace":[77,101],"tree":[78,102],"multiplier":[79],"temptation":[82],"designer.":[85],"Therefore,":[86],"mixed":[88],"architecture,":[89],"both":[91,104],"traditional":[92],"techniques":[95],"proposed,":[97],"which":[98],"outperforms":[99],"in":[103],"consumption":[106],"timing,":[108],"with":[109],"15%-20%":[111],"extra":[112],"penalty":[114]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":3}],"updated_date":"2026-03-20T23:20:44.827607","created_date":"2025-10-10T00:00:00"}
