{"id":"https://openalex.org/W2145036677","doi":"https://doi.org/10.1109/iscas.2006.1692858","title":"A Current Copying Structure for Current-mode monotonic Digital-to-Analog converters","display_name":"A Current Copying Structure for Current-mode monotonic Digital-to-Analog converters","publication_year":2006,"publication_date":"2006-09-22","ids":{"openalex":"https://openalex.org/W2145036677","doi":"https://doi.org/10.1109/iscas.2006.1692858","mag":"2145036677"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2006.1692858","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2006.1692858","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5038441314","display_name":"J.L. Merino","orcid":null},"institutions":[{"id":"https://openalex.org/I134820265","display_name":"Consejo Superior de Investigaciones Cient\u00edficas","ror":"https://ror.org/02gfc7t72","country_code":"ES","type":"funder","lineage":["https://openalex.org/I134820265"]}],"countries":["ES"],"is_corresponding":true,"raw_author_name":"J.L. Merino","raw_affiliation_strings":["Electronic circuits design group,CNM, CSIC, Bellaterra, Spain"],"affiliations":[{"raw_affiliation_string":"Electronic circuits design group,CNM, CSIC, Bellaterra, Spain","institution_ids":["https://openalex.org/I134820265"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5007355640","display_name":"Llu\u00eds Ter\u00e9s","orcid":"https://orcid.org/0000-0002-9263-411X"},"institutions":[{"id":"https://openalex.org/I134820265","display_name":"Consejo Superior de Investigaciones Cient\u00edficas","ror":"https://ror.org/02gfc7t72","country_code":"ES","type":"funder","lineage":["https://openalex.org/I134820265"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"L. Teres","raw_affiliation_strings":["Electronic circuits design group,CNM, CSIC, Bellaterra, Spain"],"affiliations":[{"raw_affiliation_string":"Electronic circuits design group,CNM, CSIC, Bellaterra, Spain","institution_ids":["https://openalex.org/I134820265"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5055631615","display_name":"Jordi Carrabina","orcid":"https://orcid.org/0000-0002-9540-8759"},"institutions":[{"id":"https://openalex.org/I123044942","display_name":"Universitat Aut\u00f2noma de Barcelona","ror":"https://ror.org/052g8jq94","country_code":"ES","type":"education","lineage":["https://openalex.org/I123044942"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"J. Carrabina","raw_affiliation_strings":["Department of Microelectronic and Electronic Systems, University Aut\u00f2noma de Barcelona, Barcelona, Spain"],"affiliations":[{"raw_affiliation_string":"Department of Microelectronic and Electronic Systems, University Aut\u00f2noma de Barcelona, Barcelona, Spain","institution_ids":["https://openalex.org/I123044942"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5038441314"],"corresponding_institution_ids":["https://openalex.org/I134820265"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.18778354,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"1","issue":null,"first_page":"1406","last_page":"1409"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9969000220298767,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9965999722480774,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/least-significant-bit","display_name":"Least significant bit","score":0.6914993524551392},{"id":"https://openalex.org/keywords/converters","display_name":"Converters","score":0.648379385471344},{"id":"https://openalex.org/keywords/current","display_name":"Current (fluid)","score":0.6219881176948547},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.5584574937820435},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5407095551490784},{"id":"https://openalex.org/keywords/digital-to-analog-converter","display_name":"Digital-to-analog converter","score":0.5381186604499817},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.5205315351486206},{"id":"https://openalex.org/keywords/current-mirror","display_name":"Current mirror","score":0.5174539685249329},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.47315630316734314},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.44611436128616333},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.443970263004303},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.44201192259788513},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.25264307856559753},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.24608063697814941},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.23566368222236633},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.16728347539901733}],"concepts":[{"id":"https://openalex.org/C4305246","wikidata":"https://www.wikidata.org/wiki/Q3885225","display_name":"Least significant bit","level":2,"score":0.6914993524551392},{"id":"https://openalex.org/C2778422915","wikidata":"https://www.wikidata.org/wiki/Q10302051","display_name":"Converters","level":3,"score":0.648379385471344},{"id":"https://openalex.org/C148043351","wikidata":"https://www.wikidata.org/wiki/Q4456944","display_name":"Current (fluid)","level":2,"score":0.6219881176948547},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.5584574937820435},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5407095551490784},{"id":"https://openalex.org/C2779879419","wikidata":"https://www.wikidata.org/wiki/Q210863","display_name":"Digital-to-analog converter","level":3,"score":0.5381186604499817},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.5205315351486206},{"id":"https://openalex.org/C173966970","wikidata":"https://www.wikidata.org/wiki/Q786012","display_name":"Current mirror","level":4,"score":0.5174539685249329},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.47315630316734314},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.44611436128616333},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.443970263004303},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.44201192259788513},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.25264307856559753},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.24608063697814941},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.23566368222236633},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.16728347539901733},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2006.1692858","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2006.1692858","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.6700000166893005,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W1906659473","https://openalex.org/W1989701455","https://openalex.org/W2102513253","https://openalex.org/W2152888666","https://openalex.org/W2169973530","https://openalex.org/W6684862703"],"related_works":["https://openalex.org/W2161636646","https://openalex.org/W2531966977","https://openalex.org/W2028124978","https://openalex.org/W3047535274","https://openalex.org/W2140339712","https://openalex.org/W2128105232","https://openalex.org/W1974076325","https://openalex.org/W1485569964","https://openalex.org/W2470509965","https://openalex.org/W2078936369"],"abstract_inverted_index":{"This":[0],"paper":[1],"describes":[2],"a":[3,60,74],"12-bit":[4],"current":[5,19,26,52],"mode":[6],"digital":[7],"to":[8,28,32,48],"analog":[9],"converter.":[10],"Circuit":[11],"topology":[12,43],"uses":[13],"two":[14],"arrays":[15],"of":[16,41,63,83],"64":[17],"equal":[18],"sources,":[20],"each":[21],"one":[22],"generating":[23],"both":[24],"the":[25,45,50,55,64],"associated":[27],"six":[29],"bits,":[30],"corresponding":[31],"either":[33],"MSB":[34],"or":[35],"LSB":[36,56],"parts.":[37],"The":[38,66],"main":[39],"novelty":[40],"that":[42],"is":[44],"method":[46],"used":[47],"limit":[49],"maximum":[51],"provided":[53],"by":[54],"block,":[57],"which":[58],"ensures":[59],"monotonic":[61],"behavior":[62],"system.":[65],"circuit":[67],"has":[68],"been":[69],"designed":[70],"and":[71,79],"fabricated":[72],"using":[73],"0.35":[75],"mum":[76],"CMOS":[77],"process":[78],"occupies":[80],"an":[81],"area":[82],"0.17":[84],"mm":[85],"<sup":[86],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[87],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[88]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
