{"id":"https://openalex.org/W1579759618","doi":"https://doi.org/10.1109/iscas.2006.1692771","title":"A Design Strategy for VHF Filters with Digital Programmability","display_name":"A Design Strategy for VHF Filters with Digital Programmability","publication_year":2006,"publication_date":"2006-09-22","ids":{"openalex":"https://openalex.org/W1579759618","doi":"https://doi.org/10.1109/iscas.2006.1692771","mag":"1579759618"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2006.1692771","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2006.1692771","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5027161966","display_name":"A. Ot\u00edn","orcid":"https://orcid.org/0000-0003-1403-1505"},"institutions":[{"id":"https://openalex.org/I255234318","display_name":"Universidad de Zaragoza","ror":"https://ror.org/012a91z28","country_code":"ES","type":"education","lineage":["https://openalex.org/I255234318"]}],"countries":["ES"],"is_corresponding":true,"raw_author_name":"A. Otin","raw_affiliation_strings":["Group of Electronics Design, GDE-CDAM, University of Zaragoza, Zaragoza, Spain","Group of Electron. Design, Zaragoza Univ., Spain"],"affiliations":[{"raw_affiliation_string":"Group of Electronics Design, GDE-CDAM, University of Zaragoza, Zaragoza, Spain","institution_ids":["https://openalex.org/I255234318"]},{"raw_affiliation_string":"Group of Electron. Design, Zaragoza Univ., Spain","institution_ids":["https://openalex.org/I255234318"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5075718351","display_name":"S. Celma","orcid":"https://orcid.org/0000-0003-0182-7723"},"institutions":[{"id":"https://openalex.org/I255234318","display_name":"Universidad de Zaragoza","ror":"https://ror.org/012a91z28","country_code":"ES","type":"education","lineage":["https://openalex.org/I255234318"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"S. Celma","raw_affiliation_strings":["Group of Electronics Design, GDE-CDAM, University of Zaragoza, Zaragoza, Spain","Group of Electron. Design, Zaragoza Univ., Spain"],"affiliations":[{"raw_affiliation_string":"Group of Electronics Design, GDE-CDAM, University of Zaragoza, Zaragoza, Spain","institution_ids":["https://openalex.org/I255234318"]},{"raw_affiliation_string":"Group of Electron. Design, Zaragoza Univ., Spain","institution_ids":["https://openalex.org/I255234318"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5047274950","display_name":"C. Aldea","orcid":"https://orcid.org/0000-0003-2874-6368"},"institutions":[{"id":"https://openalex.org/I255234318","display_name":"Universidad de Zaragoza","ror":"https://ror.org/012a91z28","country_code":"ES","type":"education","lineage":["https://openalex.org/I255234318"]}],"countries":["ES"],"is_corresponding":false,"raw_author_name":"C. Aldea","raw_affiliation_strings":["Group of Electronics Design, GDE-CDAM, University of Zaragoza, Zaragoza, Spain","Group of Electron. Design, Zaragoza Univ., Spain"],"affiliations":[{"raw_affiliation_string":"Group of Electronics Design, GDE-CDAM, University of Zaragoza, Zaragoza, Spain","institution_ids":["https://openalex.org/I255234318"]},{"raw_affiliation_string":"Group of Electron. Design, Zaragoza Univ., Spain","institution_ids":["https://openalex.org/I255234318"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5027161966"],"corresponding_institution_ids":["https://openalex.org/I255234318"],"apc_list":null,"apc_paid":null,"fwci":1.9529,"has_fulltext":false,"cited_by_count":10,"citation_normalized_percentile":{"value":0.84691492,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":96,"max":97},"biblio":{"volume":"36","issue":null,"first_page":"1059","last_page":"1062"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9986000061035156,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5117177963256836},{"id":"https://openalex.org/keywords/filter","display_name":"Filter (signal processing)","score":0.5090450644493103},{"id":"https://openalex.org/keywords/analogue-filter","display_name":"Analogue filter","score":0.508185625076294},{"id":"https://openalex.org/keywords/low-pass-filter","display_name":"Low-pass filter","score":0.500516414642334},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4796762466430664},{"id":"https://openalex.org/keywords/total-harmonic-distortion","display_name":"Total harmonic distortion","score":0.47498148679733276},{"id":"https://openalex.org/keywords/band-pass-filter","display_name":"Band-pass filter","score":0.4745034873485565},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4556051790714264},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.45517921447753906},{"id":"https://openalex.org/keywords/dynamic-range","display_name":"Dynamic range","score":0.4503915011882782},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.4373414218425751},{"id":"https://openalex.org/keywords/strips","display_name":"STRIPS","score":0.4283478260040283},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.36764779686927795},{"id":"https://openalex.org/keywords/digital-filter","display_name":"Digital filter","score":0.3414366841316223},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.32725897431373596},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2962397336959839},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.2957229018211365},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.21933245658874512},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.17222487926483154}],"concepts":[{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5117177963256836},{"id":"https://openalex.org/C106131492","wikidata":"https://www.wikidata.org/wiki/Q3072260","display_name":"Filter (signal processing)","level":2,"score":0.5090450644493103},{"id":"https://openalex.org/C176046018","wikidata":"https://www.wikidata.org/wiki/Q359205","display_name":"Analogue filter","level":4,"score":0.508185625076294},{"id":"https://openalex.org/C44682112","wikidata":"https://www.wikidata.org/wiki/Q918242","display_name":"Low-pass filter","level":3,"score":0.500516414642334},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4796762466430664},{"id":"https://openalex.org/C42156128","wikidata":"https://www.wikidata.org/wiki/Q162641","display_name":"Total harmonic distortion","level":3,"score":0.47498148679733276},{"id":"https://openalex.org/C147788027","wikidata":"https://www.wikidata.org/wiki/Q2718101","display_name":"Band-pass filter","level":2,"score":0.4745034873485565},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4556051790714264},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.45517921447753906},{"id":"https://openalex.org/C87133666","wikidata":"https://www.wikidata.org/wiki/Q1161699","display_name":"Dynamic range","level":2,"score":0.4503915011882782},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.4373414218425751},{"id":"https://openalex.org/C200925200","wikidata":"https://www.wikidata.org/wiki/Q7624170","display_name":"STRIPS","level":2,"score":0.4283478260040283},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.36764779686927795},{"id":"https://openalex.org/C36390408","wikidata":"https://www.wikidata.org/wiki/Q1163067","display_name":"Digital filter","level":3,"score":0.3414366841316223},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.32725897431373596},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2962397336959839},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.2957229018211365},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.21933245658874512},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.17222487926483154}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2006.1692771","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2006.1692771","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8299999833106995,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W29830616","https://openalex.org/W606219058","https://openalex.org/W1594936096","https://openalex.org/W2008438434","https://openalex.org/W2041026247","https://openalex.org/W2066840192","https://openalex.org/W2079065757","https://openalex.org/W2096941562","https://openalex.org/W2135433397","https://openalex.org/W2141499904","https://openalex.org/W2160115507","https://openalex.org/W2541874213"],"related_works":["https://openalex.org/W2946633907","https://openalex.org/W3000365547","https://openalex.org/W1994978815","https://openalex.org/W2182489947","https://openalex.org/W2038726274","https://openalex.org/W1992639850","https://openalex.org/W2133624256","https://openalex.org/W1999201299","https://openalex.org/W4301184722","https://openalex.org/W2317628450"],"abstract_inverted_index":{"In":[0],"this":[1],"paper":[2],"we":[3],"report":[4],"2nd":[5],"and":[6,68],"3rd-order":[7],"G":[8],"<sub":[9],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[10,112],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">m</sub>":[11],"-C":[12],"filters":[13,72],"based":[14],"on":[15],"fully-balanced":[16],"pseudo-differential":[17],"continuous-time":[18],"transconductors":[19],"for":[20,100],"applications":[21,62],"in":[22,61],"low-voltage":[23],"systems":[24,67],"over":[25,48],"the":[26,49,55,58],"VHF":[27],"range.":[28],"By":[29],"using":[30],"a":[31,44,84],"0.35":[32],"mum":[33],"standard":[34],"CMOS":[35],"process,":[36],"low-pass":[37],"filter":[38],"approximations":[39],"have":[40],"been":[41],"implemented":[42],"with":[43],"cut-off":[45],"frequency":[46],"programmability":[47],"40-200":[50],"MHz":[51,82],"range,":[52],"which":[53],"confirm":[54],"feasibility":[56],"of":[57,98],"proposed":[59],"strategy":[60],"such":[63],"as":[64],"data":[65],"storage":[66],"IF":[69],"strips.":[70],"The":[71,87,103],"consume":[73],"less":[74],"than":[75,93],"4.8":[76],"mW":[77],"per":[78,114],"pole":[79,115],"at":[80,96],"45":[81],"from":[83],"2V":[85],"supply.":[86],"measured":[88],"dynamic":[89],"range":[90],"was":[91],"better":[92],"53":[94],"dB":[95],"THD":[97],"1%":[99],"all":[101],"filters.":[102],"maximum":[104],"active":[105],"chip":[106],"area":[107],"is":[108],"0.025":[109],"mm":[110],"<sup":[111],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[113]},"counts_by_year":[{"year":2013,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
