{"id":"https://openalex.org/W2160668294","doi":"https://doi.org/10.1109/iscas.2006.1692751","title":"DCOS: cache embedded switch architecture for distributed shared memory multiprocessor SoCs","display_name":"DCOS: cache embedded switch architecture for distributed shared memory multiprocessor SoCs","publication_year":2006,"publication_date":"2006-09-22","ids":{"openalex":"https://openalex.org/W2160668294","doi":"https://doi.org/10.1109/iscas.2006.1692751","mag":"2160668294"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2006.1692751","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2006.1692751","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5067007480","display_name":"Daewook Kim","orcid":"https://orcid.org/0000-0002-1122-8727"},"institutions":[{"id":"https://openalex.org/I130238516","display_name":"University of Minnesota","ror":"https://ror.org/017zqws13","country_code":"US","type":"education","lineage":["https://openalex.org/I130238516"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Daewook Kim","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN, USA","institution_ids":["https://openalex.org/I130238516"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005237416","display_name":"Manho Kim","orcid":"https://orcid.org/0000-0002-0277-6326"},"institutions":[{"id":"https://openalex.org/I130238516","display_name":"University of Minnesota","ror":"https://ror.org/017zqws13","country_code":"US","type":"education","lineage":["https://openalex.org/I130238516"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Manho Kim","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN, USA","institution_ids":["https://openalex.org/I130238516"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5041064476","display_name":"Gerald E. Sobelman","orcid":"https://orcid.org/0000-0002-4415-7320"},"institutions":[{"id":"https://openalex.org/I130238516","display_name":"University of Minnesota","ror":"https://ror.org/017zqws13","country_code":"US","type":"education","lineage":["https://openalex.org/I130238516"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"G.E. Sobelman","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN, USA","institution_ids":["https://openalex.org/I130238516"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I130238516"],"apc_list":null,"apc_paid":null,"fwci":0.6309,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.7539558,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"4","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9984999895095825,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8462572693824768},{"id":"https://openalex.org/keywords/mpsoc","display_name":"MPSoC","score":0.6584683060646057},{"id":"https://openalex.org/keywords/cache-pollution","display_name":"Cache pollution","score":0.6016315221786499},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.5971534848213196},{"id":"https://openalex.org/keywords/cache","display_name":"Cache","score":0.5961500406265259},{"id":"https://openalex.org/keywords/cache-only-memory-architecture","display_name":"Cache-only memory architecture","score":0.565426230430603},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5149779915809631},{"id":"https://openalex.org/keywords/distributed-shared-memory","display_name":"Distributed shared memory","score":0.4985353946685791},{"id":"https://openalex.org/keywords/cache-algorithms","display_name":"Cache algorithms","score":0.4698435664176941},{"id":"https://openalex.org/keywords/bus-sniffing","display_name":"Bus sniffing","score":0.4567400813102722},{"id":"https://openalex.org/keywords/distributed-memory","display_name":"Distributed memory","score":0.45657777786254883},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4350980520248413},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.41321998834609985},{"id":"https://openalex.org/keywords/mesi-protocol","display_name":"MESI protocol","score":0.41256970167160034},{"id":"https://openalex.org/keywords/uniform-memory-access","display_name":"Uniform memory access","score":0.40885359048843384},{"id":"https://openalex.org/keywords/cpu-cache","display_name":"CPU cache","score":0.3927225172519684},{"id":"https://openalex.org/keywords/cache-coloring","display_name":"Cache coloring","score":0.37744319438934326},{"id":"https://openalex.org/keywords/multiprocessing","display_name":"Multiprocessing","score":0.3470399081707001},{"id":"https://openalex.org/keywords/memory-management","display_name":"Memory management","score":0.24669280648231506},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.23813730478286743},{"id":"https://openalex.org/keywords/overlay","display_name":"Overlay","score":0.12984061241149902}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8462572693824768},{"id":"https://openalex.org/C2777187653","wikidata":"https://www.wikidata.org/wiki/Q975106","display_name":"MPSoC","level":3,"score":0.6584683060646057},{"id":"https://openalex.org/C113166858","wikidata":"https://www.wikidata.org/wiki/Q5015981","display_name":"Cache pollution","level":5,"score":0.6016315221786499},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.5971534848213196},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.5961500406265259},{"id":"https://openalex.org/C3720319","wikidata":"https://www.wikidata.org/wiki/Q5015937","display_name":"Cache-only memory architecture","level":5,"score":0.565426230430603},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5149779915809631},{"id":"https://openalex.org/C39528615","wikidata":"https://www.wikidata.org/wiki/Q1229610","display_name":"Distributed shared memory","level":5,"score":0.4985353946685791},{"id":"https://openalex.org/C38556500","wikidata":"https://www.wikidata.org/wiki/Q13404475","display_name":"Cache algorithms","level":4,"score":0.4698435664176941},{"id":"https://openalex.org/C51185590","wikidata":"https://www.wikidata.org/wiki/Q1017228","display_name":"Bus sniffing","level":5,"score":0.4567400813102722},{"id":"https://openalex.org/C91481028","wikidata":"https://www.wikidata.org/wiki/Q1054686","display_name":"Distributed memory","level":3,"score":0.45657777786254883},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4350980520248413},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.41321998834609985},{"id":"https://openalex.org/C120936851","wikidata":"https://www.wikidata.org/wiki/Q1408065","display_name":"MESI protocol","level":5,"score":0.41256970167160034},{"id":"https://openalex.org/C51290061","wikidata":"https://www.wikidata.org/wiki/Q1936765","display_name":"Uniform memory access","level":4,"score":0.40885359048843384},{"id":"https://openalex.org/C189783530","wikidata":"https://www.wikidata.org/wiki/Q352090","display_name":"CPU cache","level":3,"score":0.3927225172519684},{"id":"https://openalex.org/C201148951","wikidata":"https://www.wikidata.org/wiki/Q5015976","display_name":"Cache coloring","level":4,"score":0.37744319438934326},{"id":"https://openalex.org/C4822641","wikidata":"https://www.wikidata.org/wiki/Q846651","display_name":"Multiprocessing","level":2,"score":0.3470399081707001},{"id":"https://openalex.org/C176649486","wikidata":"https://www.wikidata.org/wiki/Q2308807","display_name":"Memory management","level":3,"score":0.24669280648231506},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.23813730478286743},{"id":"https://openalex.org/C136085584","wikidata":"https://www.wikidata.org/wiki/Q910289","display_name":"Overlay","level":2,"score":0.12984061241149902}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iscas.2006.1692751","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2006.1692751","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.132.1502","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.132.1502","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://mountains.ece.umn.edu/~sobelman/papers/dcos_iscas06.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1769402780","https://openalex.org/W1850405760","https://openalex.org/W1980257390","https://openalex.org/W2025816492","https://openalex.org/W2126372249","https://openalex.org/W2128728233","https://openalex.org/W2145021036","https://openalex.org/W2157447097","https://openalex.org/W2162434736","https://openalex.org/W2417497656","https://openalex.org/W4229823398"],"related_works":["https://openalex.org/W2781952239","https://openalex.org/W2243652835","https://openalex.org/W2148887883","https://openalex.org/W2394669314","https://openalex.org/W2764760984","https://openalex.org/W2407815036","https://openalex.org/W2144789089","https://openalex.org/W2105141138","https://openalex.org/W1545683692","https://openalex.org/W1768902350"],"abstract_inverted_index":{"Shared":[0],"memory":[1,27],"is":[2,49],"a":[3,22,35,63,87],"common":[4],"inter-processor":[5],"communication":[6],"paradigm":[7],"for":[8],"on-chip":[9],"multiprocessor":[10],"SoC":[11],"(MPSoC)":[12],"platforms.":[13],"The":[14],"latency":[15],"overhead":[16],"of":[17,55],"switch-based":[18],"interconnection":[19],"networks":[20],"plays":[21],"critical":[23],"role":[24],"in":[25,62,65,89,96],"shared":[26,42,46],"MPSoC":[28],"designs.":[29],"In":[30],"this":[31],"paper,":[32],"we":[33],"propose":[34],"directory-cache":[36],"embedded":[37,95],"switch":[38],"architecture":[39],"with":[40],"distributed":[41,45],"cache":[43,58],"and":[44,70],"memory.":[47],"It":[48],"able":[50],"to":[51],"reduce":[52],"the":[53,66,71,79,97],"number":[54],"home":[56],"node":[57],"accesses,":[59],"which":[60,90],"results":[61,76],"reduction":[64],"inter-cache":[67],"transfer":[68],"time":[69],"total":[72],"execution":[73],"time.":[74],"Simulation":[75],"verify":[77],"that":[78],"proposed":[80],"methodology":[81],"can":[82],"improve":[83],"performance":[84],"substantially":[85],"over":[86],"design":[88],"directory":[91],"caches":[92],"are":[93],"not":[94],"switches.":[98]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}
