{"id":"https://openalex.org/W1533953008","doi":"https://doi.org/10.1109/iscas.2006.1692698","title":"Delay Uncertainty Due to Supply Variations in Static and Dynamic Full Adders","display_name":"Delay Uncertainty Due to Supply Variations in Static and Dynamic Full Adders","publication_year":2006,"publication_date":"2006-09-22","ids":{"openalex":"https://openalex.org/W1533953008","doi":"https://doi.org/10.1109/iscas.2006.1692698","mag":"1533953008"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2006.1692698","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2006.1692698","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5052037141","display_name":"Massimo Alioto","orcid":"https://orcid.org/0000-0002-4127-8258"},"institutions":[{"id":"https://openalex.org/I102064193","display_name":"University of Siena","ror":"https://ror.org/01tevnk56","country_code":"IT","type":"education","lineage":["https://openalex.org/I102064193"]}],"countries":["IT"],"is_corresponding":true,"raw_author_name":"M. Alioto","raw_affiliation_strings":["DII-Dipartimento di Ingegneria dell'Informazione, Universit\u00e0 di Siena, Siena, Italy"],"affiliations":[{"raw_affiliation_string":"DII-Dipartimento di Ingegneria dell'Informazione, Universit\u00e0 di Siena, Siena, Italy","institution_ids":["https://openalex.org/I102064193"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5044422028","display_name":"G. Palumbo","orcid":"https://orcid.org/0000-0002-8011-8660"},"institutions":[{"id":"https://openalex.org/I102064193","display_name":"University of Siena","ror":"https://ror.org/01tevnk56","country_code":"IT","type":"education","lineage":["https://openalex.org/I102064193"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"G. Palumbo","raw_affiliation_strings":["DIEES-Dipartimento di Ingegneria Elettrica Elettronica e dei Sistemi, Universit\u00e0 di Siena, Catania, Italy"],"affiliations":[{"raw_affiliation_string":"DIEES-Dipartimento di Ingegneria Elettrica Elettronica e dei Sistemi, Universit\u00e0 di Siena, Catania, Italy","institution_ids":["https://openalex.org/I102064193"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5052037141"],"corresponding_institution_ids":["https://openalex.org/I102064193"],"apc_list":null,"apc_paid":null,"fwci":0.3761,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.61611311,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"767","last_page":"770"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.9257539510726929},{"id":"https://openalex.org/keywords/spice","display_name":"Spice","score":0.6307884454727173},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.608923614025116},{"id":"https://openalex.org/keywords/domino-logic","display_name":"Domino logic","score":0.5824042558670044},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5752567052841187},{"id":"https://openalex.org/keywords/domino","display_name":"Domino","score":0.5113653540611267},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.44722333550453186},{"id":"https://openalex.org/keywords/sensitivity","display_name":"Sensitivity (control systems)","score":0.4297179877758026},{"id":"https://openalex.org/keywords/network-topology","display_name":"Network topology","score":0.42532363533973694},{"id":"https://openalex.org/keywords/dual","display_name":"Dual (grammatical number)","score":0.4206077456474304},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.39448612928390503},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.28667116165161133},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.26685869693756104},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.22418764233589172},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.16271337866783142},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.15073871612548828},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.10659453272819519}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.9257539510726929},{"id":"https://openalex.org/C2780077345","wikidata":"https://www.wikidata.org/wiki/Q16891888","display_name":"Spice","level":2,"score":0.6307884454727173},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.608923614025116},{"id":"https://openalex.org/C2777555262","wikidata":"https://www.wikidata.org/wiki/Q173391","display_name":"Domino logic","level":5,"score":0.5824042558670044},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5752567052841187},{"id":"https://openalex.org/C2776416436","wikidata":"https://www.wikidata.org/wiki/Q3751781","display_name":"Domino","level":3,"score":0.5113653540611267},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.44722333550453186},{"id":"https://openalex.org/C21200559","wikidata":"https://www.wikidata.org/wiki/Q7451068","display_name":"Sensitivity (control systems)","level":2,"score":0.4297179877758026},{"id":"https://openalex.org/C199845137","wikidata":"https://www.wikidata.org/wiki/Q145490","display_name":"Network topology","level":2,"score":0.42532363533973694},{"id":"https://openalex.org/C2780980858","wikidata":"https://www.wikidata.org/wiki/Q110022","display_name":"Dual (grammatical number)","level":2,"score":0.4206077456474304},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.39448612928390503},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.28667116165161133},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.26685869693756104},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22418764233589172},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.16271337866783142},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.15073871612548828},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.10659453272819519},{"id":"https://openalex.org/C185592680","wikidata":"https://www.wikidata.org/wiki/Q2329","display_name":"Chemistry","level":0,"score":0.0},{"id":"https://openalex.org/C161790260","wikidata":"https://www.wikidata.org/wiki/Q82264","display_name":"Catalysis","level":2,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C55493867","wikidata":"https://www.wikidata.org/wiki/Q7094","display_name":"Biochemistry","level":1,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C124952713","wikidata":"https://www.wikidata.org/wiki/Q8242","display_name":"Literature","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/iscas.2006.1692698","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2006.1692698","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},{"id":"pmh:oai:usiena-air.unisi.it:11365/17326","is_oa":false,"landing_page_url":"http://hdl.handle.net/11365/17326","pdf_url":null,"source":{"id":"https://openalex.org/S4377196319","display_name":"Use Siena air (University of Siena)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I102064193","host_organization_name":"University of Siena","host_organization_lineage":["https://openalex.org/I102064193"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"info:eu-repo/semantics/conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.7300000190734863,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1993091105","https://openalex.org/W1993589577","https://openalex.org/W2106006800","https://openalex.org/W2134067926","https://openalex.org/W2156749158","https://openalex.org/W2163527337","https://openalex.org/W2476075474","https://openalex.org/W2629157711","https://openalex.org/W3150625878","https://openalex.org/W4212961314","https://openalex.org/W4230566481","https://openalex.org/W4233794767"],"related_works":["https://openalex.org/W4231158717","https://openalex.org/W3174071739","https://openalex.org/W2150513440","https://openalex.org/W2168226525","https://openalex.org/W4254482168","https://openalex.org/W18274992","https://openalex.org/W2100009051","https://openalex.org/W4235278986","https://openalex.org/W4387736942","https://openalex.org/W2074296439"],"abstract_inverted_index":{"In":[0,18,73],"this":[1],"paper,":[2],"the":[3,27,34,39,55,60,75,78,86,89],"delay":[4,28,61],"uncertainty":[5,62],"due":[6,63],"to":[7,30,64],"supply":[8,31,65,90],"variations":[9,32,82],"is":[10,21,46,83,96],"investigated":[11],"for":[12,33,53],"two":[13],"important":[14],"full":[15],"adder":[16,37],"topologies.":[17],"particular,":[19,74],"it":[20],"developed":[22],"an":[23],"analytical":[24],"model":[25,45],"of":[26,77,88],"sensitivity":[29],"static":[35],"mirror":[36],"and":[38,48,51,85,93,107],"dynamic":[40],"dual-rail":[41],"domino":[42],"adder.":[43],"The":[44],"general":[47],"very":[49],"simple,":[50],"allows":[52],"identifying":[54],"main":[56],"parameters":[57],"which":[58],"define":[59],"variations,":[66],"as":[67,69],"well":[68],"deriving":[70],"design":[71],"considerations.":[72],"importance":[76],"input":[79],"rise/fall":[80],"time":[81],"clarified,":[84],"effect":[87],"voltage":[91],"reduction":[92],"technology":[94,110],"scaling":[95],"discussed.":[97],"Results":[98],"are":[99],"validated":[100],"through":[101],"SPICE":[102],"simulations":[103],"with":[104],"a":[105,108],"0.18-mum":[106],"0.35-mum":[109]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
