{"id":"https://openalex.org/W1957838347","doi":"https://doi.org/10.1109/iscas.2006.1692637","title":"An FPGA implementation of the flexible triangle search algorithm for block based motion estimation","display_name":"An FPGA implementation of the flexible triangle search algorithm for block based motion estimation","publication_year":2006,"publication_date":"2006-09-22","ids":{"openalex":"https://openalex.org/W1957838347","doi":"https://doi.org/10.1109/iscas.2006.1692637","mag":"1957838347"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2006.1692637","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2006.1692637","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5004723589","display_name":"Mohamed Rehan","orcid":"https://orcid.org/0009-0009-2256-9808"},"institutions":[{"id":"https://openalex.org/I71270174","display_name":"Victoria University","ror":"https://ror.org/04j757h98","country_code":"AU","type":"education","lineage":["https://openalex.org/I71270174"]},{"id":"https://openalex.org/I212119943","display_name":"University of Victoria","ror":"https://ror.org/04s5mat29","country_code":"CA","type":"education","lineage":["https://openalex.org/I212119943"]}],"countries":["AU","CA"],"is_corresponding":true,"raw_author_name":"M. Rehan","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Victoria, Victoria, BC, Canada","Dept of Electr. & Comput. Eng., Victoria Univ., BC"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Victoria, Victoria, BC, Canada","institution_ids":["https://openalex.org/I212119943"]},{"raw_affiliation_string":"Dept of Electr. & Comput. Eng., Victoria Univ., BC","institution_ids":["https://openalex.org/I71270174"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5056943013","display_name":"M. Watheq El\u2010Kharashi","orcid":"https://orcid.org/0000-0002-6033-733X"},"institutions":[{"id":"https://openalex.org/I71270174","display_name":"Victoria University","ror":"https://ror.org/04j757h98","country_code":"AU","type":"education","lineage":["https://openalex.org/I71270174"]},{"id":"https://openalex.org/I212119943","display_name":"University of Victoria","ror":"https://ror.org/04s5mat29","country_code":"CA","type":"education","lineage":["https://openalex.org/I212119943"]}],"countries":["AU","CA"],"is_corresponding":false,"raw_author_name":"M. Watheq El-Kharashi","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Victoria, Victoria, BC, Canada","Dept of Electr. & Comput. Eng., Victoria Univ., BC"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Victoria, Victoria, BC, Canada","institution_ids":["https://openalex.org/I212119943"]},{"raw_affiliation_string":"Dept of Electr. & Comput. Eng., Victoria Univ., BC","institution_ids":["https://openalex.org/I71270174"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052682615","display_name":"P. Agathoklis","orcid":"https://orcid.org/0000-0002-2897-0549"},"institutions":[{"id":"https://openalex.org/I71270174","display_name":"Victoria University","ror":"https://ror.org/04j757h98","country_code":"AU","type":"education","lineage":["https://openalex.org/I71270174"]},{"id":"https://openalex.org/I212119943","display_name":"University of Victoria","ror":"https://ror.org/04s5mat29","country_code":"CA","type":"education","lineage":["https://openalex.org/I212119943"]}],"countries":["AU","CA"],"is_corresponding":false,"raw_author_name":"P. Agathoklis","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Victoria, Victoria, BC, Canada","Dept of Electr. & Comput. Eng., Victoria Univ., BC"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Victoria, Victoria, BC, Canada","institution_ids":["https://openalex.org/I212119943"]},{"raw_affiliation_string":"Dept of Electr. & Comput. Eng., Victoria Univ., BC","institution_ids":["https://openalex.org/I71270174"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5014237424","display_name":"Fayez Gebali","orcid":"https://orcid.org/0000-0001-5189-3409"},"institutions":[{"id":"https://openalex.org/I212119943","display_name":"University of Victoria","ror":"https://ror.org/04s5mat29","country_code":"CA","type":"education","lineage":["https://openalex.org/I212119943"]},{"id":"https://openalex.org/I71270174","display_name":"Victoria University","ror":"https://ror.org/04j757h98","country_code":"AU","type":"education","lineage":["https://openalex.org/I71270174"]}],"countries":["AU","CA"],"is_corresponding":false,"raw_author_name":"F. Gebali","raw_affiliation_strings":["Department of Electrical and Computer Engineering, University of Victoria, Victoria, BC, Canada","Dept of Electr. & Comput. Eng., Victoria Univ., BC"],"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering, University of Victoria, Victoria, BC, Canada","institution_ids":["https://openalex.org/I212119943"]},{"raw_affiliation_string":"Dept of Electr. & Comput. Eng., Victoria Univ., BC","institution_ids":["https://openalex.org/I71270174"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5004723589"],"corresponding_institution_ids":["https://openalex.org/I212119943","https://openalex.org/I71270174"],"apc_list":null,"apc_paid":null,"fwci":2.2263,"has_fulltext":false,"cited_by_count":19,"citation_normalized_percentile":{"value":0.86780193,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"2","issue":null,"first_page":"4","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10741","display_name":"Video Coding and Compression Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10741","display_name":"Video Coding and Compression Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1711","display_name":"Signal Processing"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10531","display_name":"Advanced Vision and Imaging","score":0.9990000128746033,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10901","display_name":"Advanced Data Compression Techniques","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8348665237426758},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7881327271461487},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.6784875392913818},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.6691708564758301},{"id":"https://openalex.org/keywords/motion-estimation","display_name":"Motion estimation","score":0.6059064865112305},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.520172119140625},{"id":"https://openalex.org/keywords/data-compression","display_name":"Data compression","score":0.49221888184547424},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.47869423031806946},{"id":"https://openalex.org/keywords/matching","display_name":"Matching (statistics)","score":0.4507930874824524},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3593481481075287},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.09388074278831482}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8348665237426758},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7881327271461487},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.6784875392913818},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.6691708564758301},{"id":"https://openalex.org/C10161872","wikidata":"https://www.wikidata.org/wiki/Q557891","display_name":"Motion estimation","level":2,"score":0.6059064865112305},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.520172119140625},{"id":"https://openalex.org/C78548338","wikidata":"https://www.wikidata.org/wiki/Q2493","display_name":"Data compression","level":2,"score":0.49221888184547424},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.47869423031806946},{"id":"https://openalex.org/C165064840","wikidata":"https://www.wikidata.org/wiki/Q1321061","display_name":"Matching (statistics)","level":2,"score":0.4507930874824524},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3593481481075287},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.09388074278831482},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2006.1692637","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2006.1692637","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":20,"referenced_works":["https://openalex.org/W1481550144","https://openalex.org/W1503929165","https://openalex.org/W1576703464","https://openalex.org/W1620996123","https://openalex.org/W1952436568","https://openalex.org/W1974241445","https://openalex.org/W2039181402","https://openalex.org/W2096681624","https://openalex.org/W2099124466","https://openalex.org/W2111913387","https://openalex.org/W2120624236","https://openalex.org/W2129124963","https://openalex.org/W2132614232","https://openalex.org/W2136760469","https://openalex.org/W2141109916","https://openalex.org/W2148692161","https://openalex.org/W2165128265","https://openalex.org/W2170937519","https://openalex.org/W6629976245","https://openalex.org/W6636784688"],"related_works":["https://openalex.org/W2383333355","https://openalex.org/W3004362061","https://openalex.org/W2364622490","https://openalex.org/W2042515040","https://openalex.org/W2383986884","https://openalex.org/W2356141508","https://openalex.org/W4297665406","https://openalex.org/W1735031787","https://openalex.org/W2749962643","https://openalex.org/W2390807153"],"abstract_inverted_index":{"In":[0,111],"this":[1,112],"paper":[2],"a":[3,23,52,62,114,118],"hardware":[4,115,202],"architecture":[5,116,128],"for":[6,27,38,117,140,185],"the":[7,10,44,69,72,77,85,88,108,122,141,155,163,175,194],"implementation":[8,120,153,166,196],"of":[9,64,90,107,121,154,170,178],"flexible":[11],"triangle":[12,54,70],"search":[13,53,157,184],"algorithm":[14,26,124],"(FTS)":[15],"using":[16,51,133,137],"FPGAs":[17],"is":[18,22,125,129,188,197],"proposed.":[19,126],"The":[20,41,145],"FTS":[21,42,86,123,164],"fast":[24,97,198],"block-matching":[25],"motion":[28,183],"estimation":[29],"proposed":[30,195],"in":[31],"previous":[32],"work,":[33],"which":[34,55],"can":[35],"be":[36],"used":[37],"video":[39],"compression.":[40],"finds":[43],"best":[45,78],"matching":[46,79,92,99],"blocks":[47],"between":[48],"two":[49],"frames":[50],"changes":[56],"its":[57],"direction":[58],"and":[59,131,135,174,199,203],"size":[60],"through":[61],"set":[63],"operations.":[65],"These":[66],"operations":[67,93],"provide":[68],"with":[71,95],"necessary":[73],"flexibility":[74],"to":[75,150,181],"locate":[76],"block.":[80],"Simulation":[81],"results":[82,146],"indicate":[83],"that":[84,162,193],"reduces":[87],"number":[89,169,177],"block":[91,98,187],"compared":[94,149],"other":[96],"algorithms":[100],"without":[101],"affecting":[102],"quality":[103],"or":[104],"compression":[105],"ratio":[106],"compressed":[109],"bitstream.":[110],"paper,":[113],"FPGA":[119,152,165],"This":[127,191],"simulated":[130],"tested":[132],"VHDL":[134],"synthesized":[136],"Xilinx":[138,142],"ISE":[139],"Spartan3":[143],"device.":[144],"obtained":[147],"were":[148],"an":[151],"full":[156],"(FS)":[158],"algorithm.":[159],"Results":[160],"indicates":[161,192],"requires":[167,200],"less":[168,201],"gates":[171],"than":[172,205],"FS":[173],"required":[176],"cycles":[179],"needed":[180],"complete":[182],"one":[186],"much":[189],"lower.":[190],"power":[204],"existing":[206],"ones.":[207]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":2},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
