{"id":"https://openalex.org/W2119412827","doi":"https://doi.org/10.1109/iscas.2006.1692579","title":"Design and Implementation of Efficient Reed-Solomon Decoders for Multi-Mode Applications","display_name":"Design and Implementation of Efficient Reed-Solomon Decoders for Multi-Mode Applications","publication_year":2006,"publication_date":"2006-09-22","ids":{"openalex":"https://openalex.org/W2119412827","doi":"https://doi.org/10.1109/iscas.2006.1692579","mag":"2119412827"},"language":"en","primary_location":{"id":"doi:10.1109/iscas.2006.1692579","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2006.1692579","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5053167526","display_name":"Ming\u2010Der Shieh","orcid":"https://orcid.org/0000-0002-7361-1860"},"institutions":[{"id":"https://openalex.org/I91807558","display_name":"National Cheng Kung University","ror":"https://ror.org/01b8kcc49","country_code":"TW","type":"education","lineage":["https://openalex.org/I91807558"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Ming-Der Shieh","raw_affiliation_strings":["Department of Electrical Engineering, National Cheng-Kung University, Tainan, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Cheng-Kung University, Tainan, Taiwan","institution_ids":["https://openalex.org/I91807558"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100869619","display_name":"Yung-Kuei Lu","orcid":null},"institutions":[{"id":"https://openalex.org/I91807558","display_name":"National Cheng Kung University","ror":"https://ror.org/01b8kcc49","country_code":"TW","type":"education","lineage":["https://openalex.org/I91807558"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yung-Kuei Lu","raw_affiliation_strings":["Department of Electrical Engineering, National Cheng-Kung University, Tainan, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Cheng-Kung University, Tainan, Taiwan","institution_ids":["https://openalex.org/I91807558"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5007257667","display_name":"Shen\u2010Ming Chung","orcid":"https://orcid.org/0000-0001-8086-6661"},"institutions":[{"id":"https://openalex.org/I4210148468","display_name":"Industrial Technology Research Institute","ror":"https://ror.org/05szzwt63","country_code":"TW","type":"nonprofit","lineage":["https://openalex.org/I4210148468"]},{"id":"https://openalex.org/I142066694","display_name":"ITRI International","ror":"https://ror.org/04wwsbd59","country_code":"US","type":"facility","lineage":["https://openalex.org/I142066694"]}],"countries":["TW","US"],"is_corresponding":false,"raw_author_name":"Shen-Ming Chung","raw_affiliation_strings":["Computer & Communications Research Labs, Industrial Technology Research Institute","Computer & Communications Research Labs, Industrial Technology Research Institute, Taiwan"],"affiliations":[{"raw_affiliation_string":"Computer & Communications Research Labs, Industrial Technology Research Institute","institution_ids":["https://openalex.org/I142066694"]},{"raw_affiliation_string":"Computer & Communications Research Labs, Industrial Technology Research Institute, Taiwan","institution_ids":["https://openalex.org/I4210148468"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100749478","display_name":"Junhong Chen","orcid":"https://orcid.org/0000-0001-5418-5993"},"institutions":[{"id":"https://openalex.org/I91807558","display_name":"National Cheng Kung University","ror":"https://ror.org/01b8kcc49","country_code":"TW","type":"education","lineage":["https://openalex.org/I91807558"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Jun-Hong Chen","raw_affiliation_strings":["Department of Electrical Engineering, National Cheng-Kung University, Tainan, Taiwan","Department of Electrical Engineering, National Engineering Kung University, Tainan, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Cheng-Kung University, Tainan, Taiwan","institution_ids":["https://openalex.org/I91807558"]},{"raw_affiliation_string":"Department of Electrical Engineering, National Engineering Kung University, Tainan, Taiwan","institution_ids":["https://openalex.org/I91807558"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5053167526"],"corresponding_institution_ids":["https://openalex.org/I91807558"],"apc_list":null,"apc_paid":null,"fwci":2.7105,"has_fulltext":false,"cited_by_count":15,"citation_normalized_percentile":{"value":0.90816364,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":"1","issue":null,"first_page":"289","last_page":"292"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11130","display_name":"Coding theory and cryptography","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11130","display_name":"Coding theory and cryptography","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11321","display_name":"Error Correcting Code Techniques","score":0.9939000010490417,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.6844119429588318},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6298746466636658},{"id":"https://openalex.org/keywords/realization","display_name":"Realization (probability)","score":0.6179702281951904},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.5711544752120972},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.491190642118454},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.45060279965400696},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.44034892320632935},{"id":"https://openalex.org/keywords/clock-rate","display_name":"Clock rate","score":0.43135398626327515},{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.42701634764671326},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.40481072664260864},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3813372254371643},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2517028748989105},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.21467825770378113},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.14621543884277344},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1248687207698822},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09167999029159546}],"concepts":[{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.6844119429588318},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6298746466636658},{"id":"https://openalex.org/C2781089630","wikidata":"https://www.wikidata.org/wiki/Q21856745","display_name":"Realization (probability)","level":2,"score":0.6179702281951904},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.5711544752120972},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.491190642118454},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.45060279965400696},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.44034892320632935},{"id":"https://openalex.org/C178693496","wikidata":"https://www.wikidata.org/wiki/Q911691","display_name":"Clock rate","level":3,"score":0.43135398626327515},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.42701634764671326},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.40481072664260864},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3813372254371643},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2517028748989105},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.21467825770378113},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.14621543884277344},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1248687207698822},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09167999029159546},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/iscas.2006.1692579","is_oa":false,"landing_page_url":"https://doi.org/10.1109/iscas.2006.1692579","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2006 IEEE International Symposium on Circuits and Systems","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/9","score":0.49000000953674316,"display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W1496108277","https://openalex.org/W1556360121","https://openalex.org/W1589190557","https://openalex.org/W1593683169","https://openalex.org/W1594652978","https://openalex.org/W1777245162","https://openalex.org/W2075850503","https://openalex.org/W2083005904","https://openalex.org/W2099212663","https://openalex.org/W2116607741","https://openalex.org/W2116720352","https://openalex.org/W2134677306","https://openalex.org/W6633414894"],"related_works":["https://openalex.org/W4283025278","https://openalex.org/W2014709025","https://openalex.org/W2081032080","https://openalex.org/W2134733504","https://openalex.org/W2765822612","https://openalex.org/W2144460576","https://openalex.org/W2163915119","https://openalex.org/W1572837867","https://openalex.org/W2141748053","https://openalex.org/W2031051084"],"abstract_inverted_index":{"We":[0],"present":[1],"a":[2],"multi-mode":[3,31],"Reed-Solomon":[4],"decoder":[5,68],"based":[6,104],"on":[7,105],"the":[8,16,20,28,33,61,66,86,93,101],"reformulated":[9,21],"inversionless":[10],"Berlekamp-Massey":[11],"algorithm,":[12,108],"which":[13],"can":[14,118],"retain":[15],"throughput":[17,63],"rate":[18,64,89],"of":[19,65,90],"architecture":[22],"in":[23,77],"many":[24],"practical":[25],"applications.":[26,123],"With":[27],"developed":[29,67],"coefficient-selector-free":[30],"arrangement,":[32],"resulting":[34],"design":[35],"possesses":[36],"not":[37],"only":[38],"area-efficient":[39],"property":[40],"but":[41],"also":[42],"very":[43,52],"simple":[44],"and":[45,72,92,114,117],"regular":[46],"interconnect":[47],"topology":[48],"that":[49,60],"makes":[50],"it":[51],"suitable":[53],"for":[54,69,121],"VLSI":[55],"realization.":[56],"Implementation":[57],"results":[58],"exhibit":[59],"achievable":[62],"n/spl":[70],"les/255":[71],"0/spl":[73],"les/t/spl":[74],"les/8,":[75],"implemented":[76],"UMC":[78],"0.18/spl":[79],"mu/m":[80],"1P6M":[81],"process,":[82],"is":[83,97],"3.2Gbps":[84],"at":[85],"maximum":[87],"clock":[88],"400MHz":[91],"total":[94],"gate":[95],"count":[96],"22,931.":[98],"Compared":[99],"with":[100],"existing":[102],"work":[103],"extended":[106],"Euclidean":[107],"our":[109],"development":[110],"provides":[111],"both":[112],"area":[113],"speed":[115],"advantages":[116],"be":[119],"used":[120],"multi-standard":[122]},"counts_by_year":[{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2012,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}